Christopher Veraa

Array ( [id] => 1060086 [patent_doc_number] => 06853033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'Power MOSFET having enhanced breakdown voltage' [patent_app_type] => utility [patent_app_number] => 10/162137 [patent_app_country] => US [patent_app_date] => 2002-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 5282 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/853/06853033.pdf [firstpage_image] =>[orig_patent_app_number] => 10162137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6261101 [patent_doc_number] => 20020187755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Semiconductor switching device' [patent_app_type] => new [patent_app_number] => 10/153857 [patent_app_country] => US [patent_app_date] => 2002-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4605 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20020187755.pdf [firstpage_image] =>[orig_patent_app_number] => 10153857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7174051 [patent_doc_number] => 20040201044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Semiconductor structure and method for improving its ability to withstand electrostatic discharge (esd) and overloads' [patent_app_type] => new [patent_app_number] => 10/479267 [patent_app_country] => US [patent_app_date] => 2004-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5068 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20040201044.pdf [firstpage_image] =>[orig_patent_app_number] => 10479267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6848312 [patent_doc_number] => 20030140514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'Scribe lines for increasing wafer utilizable area' [patent_app_type] => new [patent_app_number] => 10/063887 [patent_app_country] => US [patent_app_date] => 2002-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2642 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20030140514.pdf [firstpage_image] =>[orig_patent_app_number] => 10063887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1221676 [patent_doc_number] => 06703649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-09 [patent_title] => 'Semiconductor element' [patent_app_type] => B2 [patent_app_number] => 10/147047 [patent_app_country] => US [patent_app_date] => 2002-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3619 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/703/06703649.pdf [firstpage_image] =>[orig_patent_app_number] => 10147047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6688515 [patent_doc_number] => 20030032240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Semiconductor memory device having a multiple tunnel junction layer pattern and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/146897 [patent_app_country] => US [patent_app_date] => 2002-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4857 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20030032240.pdf [firstpage_image] =>[orig_patent_app_number] => 10146897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1302110 [patent_doc_number] => 06624446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-23 [patent_title] => 'Thin film transistor for liquid crystal display and method of manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 10/142977 [patent_app_country] => US [patent_app_date] => 2002-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 60 [patent_no_of_words] => 10672 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624446.pdf [firstpage_image] =>[orig_patent_app_number] => 10142977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1272675 [patent_doc_number] => 06653664 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Bandgap engineering of tfel devices' [patent_app_type] => B1 [patent_app_number] => 10/139291 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1934 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653664.pdf [firstpage_image] =>[orig_patent_app_number] => 10139291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6723403 [patent_doc_number] => 20030205715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'HETEROJUNCTION P-I-N DIODE AND METHOD OF MAKING THE SAME' [patent_app_type] => new [patent_app_number] => 10/139067 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4726 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20030205715.pdf [firstpage_image] =>[orig_patent_app_number] => 10139067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5844522 [patent_doc_number] => 20020132406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'High-voltage transistor with JFET conduction channels' [patent_app_type] => new [patent_app_number] => 10/137762 [patent_app_country] => US [patent_app_date] => 2002-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6703 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20020132406.pdf [firstpage_image] =>[orig_patent_app_number] => 10137762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1384562 [patent_doc_number] => 06559513 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Field-plate MESFET' [patent_app_type] => B1 [patent_app_number] => 10/127187 [patent_app_country] => US [patent_app_date] => 2002-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4273 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559513.pdf [firstpage_image] =>[orig_patent_app_number] => 10127187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1254260 [patent_doc_number] => 06670670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-30 [patent_title] => 'Single electron memory device comprising quantum dots between gate electrode and single electron storage element and method for manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 10/125597 [patent_app_country] => US [patent_app_date] => 2002-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6568 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/670/06670670.pdf [firstpage_image] =>[orig_patent_app_number] => 10125597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1417128 [patent_doc_number] => 06528862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Bipolar transistor with a box-type germanium profile that lies outside of the emitter-base depletion region' [patent_app_type] => B1 [patent_app_number] => 10/125897 [patent_app_country] => US [patent_app_date] => 2002-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528862.pdf [firstpage_image] =>[orig_patent_app_number] => 10125897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1203372 [patent_doc_number] => 06720570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-13 [patent_title] => 'Gallium nitride-based semiconductor light emitting device' [patent_app_type] => B2 [patent_app_number] => 10/123287 [patent_app_country] => US [patent_app_date] => 2002-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5068 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/720/06720570.pdf [firstpage_image] =>[orig_patent_app_number] => 10123287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6378822 [patent_doc_number] => 20020119616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Method of manufacturing an integrated semiconductor device having a nonvolatile floating gate memory, and related integrated device' [patent_app_type] => new [patent_app_number] => 10/123507 [patent_app_country] => US [patent_app_date] => 2002-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2608 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20020119616.pdf [firstpage_image] =>[orig_patent_app_number] => 10123507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6427559 [patent_doc_number] => 20020175392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'High voltage semiconductor device having high breakdown voltage isolation region' [patent_app_type] => new [patent_app_number] => 10/123007 [patent_app_country] => US [patent_app_date] => 2002-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1950 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20020175392.pdf [firstpage_image] =>[orig_patent_app_number] => 10123007 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7963831 [patent_doc_number] => 06680512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-20 [patent_title] => 'Semiconductor device having an integral protection circuit' [patent_app_type] => B2 [patent_app_number] => 10/121447 [patent_app_country] => US [patent_app_date] => 2002-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5459 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/680/06680512.pdf [firstpage_image] =>[orig_patent_app_number] => 10121447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1249086 [patent_doc_number] => 06674109 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Nonvolatile memory' [patent_app_type] => B1 [patent_app_number] => 10/070977 [patent_app_country] => US [patent_app_date] => 2002-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3938 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/674/06674109.pdf [firstpage_image] =>[orig_patent_app_number] => 10070977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6170087 [patent_doc_number] => 20020153537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => new [patent_app_number] => 10/096057 [patent_app_country] => US [patent_app_date] => 2002-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11043 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20020153537.pdf [firstpage_image] =>[orig_patent_app_number] => 10096057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6366052 [patent_doc_number] => 20020117715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Semiconductor component for high reverse voltages in conjunction with a low on resistance and method for fabricating a semiconductor component' [patent_app_type] => new [patent_app_number] => 10/095270 [patent_app_country] => US [patent_app_date] => 2002-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4916 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20020117715.pdf [firstpage_image] =>[orig_patent_app_number] => 10095270 [rel_patent_id] =>[rel_patent_doc_number] =>)