Christopher W. Lattin

Array ( [id] => 4257985 [patent_doc_number] => 06204104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 9/195433 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 5514 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204104.pdf [firstpage_image] =>[orig_patent_app_number] => 195433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6342876 [patent_doc_number] => 20020034870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-21 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/188353 [patent_app_country] => US [patent_app_date] => 1998-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2429 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20020034870.pdf [firstpage_image] =>[orig_patent_app_number] => 09188353 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4405242 [patent_doc_number] => 06232166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'CMOS processing employing zero degree halo implant for P-channel transistor' [patent_app_type] => 1 [patent_app_number] => 9/187523 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3826 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232166.pdf [firstpage_image] =>[orig_patent_app_number] => 187523 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4095004 [patent_doc_number] => 06096629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Uniform sidewall profile etch method for forming low contact leakage schottky diode contact' [patent_app_type] => 1 [patent_app_number] => 9/187301 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 6761 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096629.pdf [firstpage_image] =>[orig_patent_app_number] => 187301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4145304 [patent_doc_number] => 06063648 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Lead formation usings grids' [patent_app_type] => 1 [patent_app_number] => 9/181901 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4601 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/063/06063648.pdf [firstpage_image] =>[orig_patent_app_number] => 181901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4116307 [patent_doc_number] => 06071752 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method of making a light reflector' [patent_app_type] => 1 [patent_app_number] => 9/179503 [patent_app_country] => US [patent_app_date] => 1998-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 2248 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071752.pdf [firstpage_image] =>[orig_patent_app_number] => 179503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4286135 [patent_doc_number] => 06211030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method for fabricating resistors in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/173703 [patent_app_country] => US [patent_app_date] => 1998-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2528 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211030.pdf [firstpage_image] =>[orig_patent_app_number] => 173703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1446589 [patent_doc_number] => 06368930 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Self aligned symmetric process and device' [patent_app_type] => B1 [patent_app_number] => 09/165203 [patent_app_country] => US [patent_app_date] => 1998-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 5968 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368930.pdf [firstpage_image] =>[orig_patent_app_number] => 09165203 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4070737 [patent_doc_number] => 06069048 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Reduction of silicon defect induced failures as a result of implants in CMOS and other integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/163623 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2128 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069048.pdf [firstpage_image] =>[orig_patent_app_number] => 163623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4235241 [patent_doc_number] => 06143593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Elevated channel MOSFET' [patent_app_type] => 1 [patent_app_number] => 9/162272 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 65 [patent_no_of_words] => 10112 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/143/06143593.pdf [firstpage_image] =>[orig_patent_app_number] => 162272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4083953 [patent_doc_number] => 06162690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Methods of forming field effect transistors having self-aligned intermediate source and drain contacts' [patent_app_type] => 1 [patent_app_number] => 9/160602 [patent_app_country] => US [patent_app_date] => 1998-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2068 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162690.pdf [firstpage_image] =>[orig_patent_app_number] => 160602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4183122 [patent_doc_number] => 06159807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Self-aligned dynamic threshold CMOS device' [patent_app_type] => 1 [patent_app_number] => 9/157691 [patent_app_country] => US [patent_app_date] => 1998-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 16 [patent_no_of_words] => 3600 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/159/06159807.pdf [firstpage_image] =>[orig_patent_app_number] => 157691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4225799 [patent_doc_number] => 06165232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Method and apparatus for securely holding a substrate during dicing' [patent_app_type] => 1 [patent_app_number] => 9/156961 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5279 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165232.pdf [firstpage_image] =>[orig_patent_app_number] => 156961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4302833 [patent_doc_number] => 06187654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Techniques for maintaining alignment of cut dies during substrate dicing' [patent_app_type] => 1 [patent_app_number] => 9/156593 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7365 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187654.pdf [firstpage_image] =>[orig_patent_app_number] => 156593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4130941 [patent_doc_number] => 06121078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Integrated circuit planarization and fill biasing design method' [patent_app_type] => 1 [patent_app_number] => 9/154652 [patent_app_country] => US [patent_app_date] => 1998-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 5010 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121078.pdf [firstpage_image] =>[orig_patent_app_number] => 154652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4141552 [patent_doc_number] => 06030863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Germanium and arsenic double implanted pre-amorphization process for salicide technology' [patent_app_type] => 1 [patent_app_number] => 9/151952 [patent_app_country] => US [patent_app_date] => 1998-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3644 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/030/06030863.pdf [firstpage_image] =>[orig_patent_app_number] => 151952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4238310 [patent_doc_number] => 06080644 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Complementary bipolar/CMOS epitaxial structure and process' [patent_app_type] => 1 [patent_app_number] => 9/149353 [patent_app_country] => US [patent_app_date] => 1998-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4345 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080644.pdf [firstpage_image] =>[orig_patent_app_number] => 149353 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170074 [patent_doc_number] => 06140253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Spin coating bowl' [patent_app_type] => 1 [patent_app_number] => 9/146691 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4840 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140253.pdf [firstpage_image] =>[orig_patent_app_number] => 146691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4214137 [patent_doc_number] => 06110761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Methods for simultaneously electrically and mechanically attaching lead frames to semiconductor dice and the resulting elements' [patent_app_type] => 1 [patent_app_number] => 9/146709 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2995 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110761.pdf [firstpage_image] =>[orig_patent_app_number] => 146709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152849 [patent_doc_number] => 06107127 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method of making shallow well MOSFET structure' [patent_app_type] => 1 [patent_app_number] => 9/145513 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 3236 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107127.pdf [firstpage_image] =>[orig_patent_app_number] => 145513 [rel_patent_id] =>[rel_patent_doc_number] =>)