Search

Christopher W. Lattin

Examiner (ID: 4104)

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
316
Issued Applications
265
Pending Applications
16
Abandoned Applications
35

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4291523 [patent_doc_number] => 06180427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method of manufacture of a thermally actuated ink jet including a tapered heater element' [patent_app_type] => 1 [patent_app_number] => 9/112832 [patent_app_country] => US [patent_app_date] => 1998-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 12434 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180427.pdf [firstpage_image] =>[orig_patent_app_number] => 112832 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/112832
Method of manufacture of a thermally actuated ink jet including a tapered heater element Jul 9, 1998 Issued
Array ( [id] => 4116283 [patent_doc_number] => 06071750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method of manufacture of a paddle type ink jet printer' [patent_app_type] => 1 [patent_app_number] => 9/113111 [patent_app_country] => US [patent_app_date] => 1998-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 14812 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071750.pdf [firstpage_image] =>[orig_patent_app_number] => 113111 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/113111
Method of manufacture of a paddle type ink jet printer Jul 9, 1998 Issued
Array ( [id] => 4206417 [patent_doc_number] => 06027961 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'CMOS semiconductor devices and method of formation' [patent_app_type] => 1 [patent_app_number] => 9/107963 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2417 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/027/06027961.pdf [firstpage_image] =>[orig_patent_app_number] => 107963 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/107963
CMOS semiconductor devices and method of formation Jun 29, 1998 Issued
09/103821 CHUCK TABLE FOR SEMICONDUCTOR WAFER Jun 23, 1998 Abandoned
Array ( [id] => 4233635 [patent_doc_number] => 06074903 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method for forming electrical isolation for semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/098203 [patent_app_country] => US [patent_app_date] => 1998-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2375 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074903.pdf [firstpage_image] =>[orig_patent_app_number] => 098203 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/098203
Method for forming electrical isolation for semiconductor devices Jun 15, 1998 Issued
Array ( [id] => 1588673 [patent_doc_number] => 06482673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-19 [patent_title] => 'Semiconductor device, method of making the same, circuit board, flexible substrate, and method of making substrate' [patent_app_type] => B2 [patent_app_number] => 09/091291 [patent_app_country] => US [patent_app_date] => 1998-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 10356 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/482/06482673.pdf [firstpage_image] =>[orig_patent_app_number] => 09091291 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/091291
Semiconductor device, method of making the same, circuit board, flexible substrate, and method of making substrate Jun 15, 1998 Issued
09/094463 RESOLUTION OF HEMISPHERICAL GRAINED SILICON PEELING AND ROW-DISTURB PROBLEMS FOR DYNAMIC RANDOM ACCESS MEMORY, STACKED CAPACITOR STRUCTURES Jun 10, 1998 Issued
Array ( [id] => 4030748 [patent_doc_number] => 05963792 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Use of an oxide surface to facilitate gate break on a carrier substrate for a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/094062 [patent_app_country] => US [patent_app_date] => 1998-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 2591 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963792.pdf [firstpage_image] =>[orig_patent_app_number] => 094062 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/094062
Use of an oxide surface to facilitate gate break on a carrier substrate for a semiconductor device Jun 8, 1998 Issued
Array ( [id] => 4172294 [patent_doc_number] => 06083783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Method of manufacturing complementary metallic-oxide-semiconductor' [patent_app_type] => 1 [patent_app_number] => 9/094053 [patent_app_country] => US [patent_app_date] => 1998-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2232 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/083/06083783.pdf [firstpage_image] =>[orig_patent_app_number] => 094053 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/094053
Method of manufacturing complementary metallic-oxide-semiconductor Jun 8, 1998 Issued
Array ( [id] => 3994266 [patent_doc_number] => 05918128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Reduced channel length for a high performance CMOS transistor' [patent_app_type] => 1 [patent_app_number] => 9/093423 [patent_app_country] => US [patent_app_date] => 1998-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4840 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918128.pdf [firstpage_image] =>[orig_patent_app_number] => 093423 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/093423
Reduced channel length for a high performance CMOS transistor Jun 7, 1998 Issued
Array ( [id] => 3937223 [patent_doc_number] => 05915199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Method for manufacturing a CMOS self-aligned strapped interconnection' [patent_app_type] => 1 [patent_app_number] => 9/090802 [patent_app_country] => US [patent_app_date] => 1998-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4458 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915199.pdf [firstpage_image] =>[orig_patent_app_number] => 090802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/090802
Method for manufacturing a CMOS self-aligned strapped interconnection Jun 3, 1998 Issued
Array ( [id] => 3976096 [patent_doc_number] => 05937286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/088072 [patent_app_country] => US [patent_app_date] => 1998-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 36 [patent_no_of_words] => 4296 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937286.pdf [firstpage_image] =>[orig_patent_app_number] => 088072 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/088072
Method for manufacturing semiconductor device May 31, 1998 Issued
Array ( [id] => 3941762 [patent_doc_number] => 05989974 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/086601 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 48 [patent_no_of_words] => 5431 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989974.pdf [firstpage_image] =>[orig_patent_app_number] => 086601 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086601
Method of manufacturing a semiconductor device May 28, 1998 Issued
09/086561 METHOD FOR MICROFABRICATING DIAMOND May 28, 1998 Issued
Array ( [id] => 4190847 [patent_doc_number] => 06043113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Method of forming self-aligned thin film transistor' [patent_app_type] => 1 [patent_app_number] => 9/000153 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2745 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043113.pdf [firstpage_image] =>[orig_patent_app_number] => 000153 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/000153
Method of forming self-aligned thin film transistor May 27, 1998 Issued
Array ( [id] => 4050766 [patent_doc_number] => 05943593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method for fabricating thin film transistor device' [patent_app_type] => 1 [patent_app_number] => 9/083926 [patent_app_country] => US [patent_app_date] => 1998-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 7015 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943593.pdf [firstpage_image] =>[orig_patent_app_number] => 083926 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/083926
Method for fabricating thin film transistor device May 21, 1998 Issued
Array ( [id] => 4419554 [patent_doc_number] => 06177325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Self-aligned emitter and base BJT process and structure' [patent_app_type] => 1 [patent_app_number] => 9/080521 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3052 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177325.pdf [firstpage_image] =>[orig_patent_app_number] => 080521 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080521
Self-aligned emitter and base BJT process and structure May 17, 1998 Issued
Array ( [id] => 4057958 [patent_doc_number] => 05909627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Process for production of thin layers of semiconductor material' [patent_app_type] => 1 [patent_app_number] => 9/080783 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1982 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909627.pdf [firstpage_image] =>[orig_patent_app_number] => 080783 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080783
Process for production of thin layers of semiconductor material May 17, 1998 Issued
Array ( [id] => 3937102 [patent_doc_number] => 05981322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Method for preventing latch-up in cmos integrated circuit devices' [patent_app_type] => 1 [patent_app_number] => 9/094043 [patent_app_country] => US [patent_app_date] => 1998-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 5074 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981322.pdf [firstpage_image] =>[orig_patent_app_number] => 094043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/094043
Method for preventing latch-up in cmos integrated circuit devices May 8, 1998 Issued
Array ( [id] => 4153188 [patent_doc_number] => 06107151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Heterojunction bipolar transistor and method of manufacturing' [patent_app_type] => 1 [patent_app_number] => 9/074652 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4026 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107151.pdf [firstpage_image] =>[orig_patent_app_number] => 074652 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/074652
Heterojunction bipolar transistor and method of manufacturing May 7, 1998 Issued
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