Search

Christopher W. Lattin

Examiner (ID: 4104)

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
316
Issued Applications
265
Pending Applications
16
Abandoned Applications
35

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4357690 [patent_doc_number] => 06191007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Method for manufacturing a semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 9/066971 [patent_app_country] => US [patent_app_date] => 1998-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 115 [patent_figures_cnt] => 378 [patent_no_of_words] => 78940 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191007.pdf [firstpage_image] =>[orig_patent_app_number] => 066971 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/066971
Method for manufacturing a semiconductor substrate Apr 27, 1998 Issued
Array ( [id] => 4037777 [patent_doc_number] => 05908309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Fabrication method of semiconductor device with CMOS structure' [patent_app_type] => 1 [patent_app_number] => 9/067861 [patent_app_country] => US [patent_app_date] => 1998-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 8145 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 377 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/908/05908309.pdf [firstpage_image] =>[orig_patent_app_number] => 067861 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/067861
Fabrication method of semiconductor device with CMOS structure Apr 27, 1998 Issued
Array ( [id] => 4116797 [patent_doc_number] => 06071786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method of manufacturing a bipolar transistor and its emitter contact' [patent_app_type] => 1 [patent_app_number] => 9/060512 [patent_app_country] => US [patent_app_date] => 1998-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1364 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071786.pdf [firstpage_image] =>[orig_patent_app_number] => 060512 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/060512
Method of manufacturing a bipolar transistor and its emitter contact Apr 13, 1998 Issued
09/057452 METHOD OF FORMING PROJECTION ELECTRODES Apr 8, 1998 Abandoned
Array ( [id] => 4204422 [patent_doc_number] => 06077723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method for fabricating a multi chip module with alignment member' [patent_app_type] => 1 [patent_app_number] => 9/053253 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 5460 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077723.pdf [firstpage_image] =>[orig_patent_app_number] => 053253 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/053253
Method for fabricating a multi chip module with alignment member Mar 31, 1998 Issued
09/048560 METHOD FOR ELECTRICALLY CONNECTING A SEMICONDUCTOR CHIP TO AT LEAST ONE CONTACT SURFACE AND SMART CARD MODULE AND SMART CARD PRODUCED BY THE METHOD Mar 25, 1998 Issued
Array ( [id] => 4030862 [patent_doc_number] => 05963799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Blanket well counter doping process for high speed/low power MOSFETs' [patent_app_type] => 1 [patent_app_number] => 9/046332 [patent_app_country] => US [patent_app_date] => 1998-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3018 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963799.pdf [firstpage_image] =>[orig_patent_app_number] => 046332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/046332
Blanket well counter doping process for high speed/low power MOSFETs Mar 22, 1998 Issued
09/046331 3-D CMOS TRANSISTORS WITH HIGH ESD RELIABILITY Mar 22, 1998 Issued
Array ( [id] => 3896380 [patent_doc_number] => 05897348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Low mask count self-aligned silicided CMOS transistors with a high electrostatic discharge resistance' [patent_app_type] => 1 [patent_app_number] => 9/042351 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3121 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 453 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/897/05897348.pdf [firstpage_image] =>[orig_patent_app_number] => 042351 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/042351
Low mask count self-aligned silicided CMOS transistors with a high electrostatic discharge resistance Mar 12, 1998 Issued
Array ( [id] => 4038134 [patent_doc_number] => 05994753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/042013 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 37 [patent_no_of_words] => 3536 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994753.pdf [firstpage_image] =>[orig_patent_app_number] => 042013 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/042013
Semiconductor device and method for fabricating the same Mar 12, 1998 Issued
Array ( [id] => 4221965 [patent_doc_number] => 06010925 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Method of making dual-gate CMOSFET' [patent_app_type] => 1 [patent_app_number] => 9/033521 [patent_app_country] => US [patent_app_date] => 1998-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2292 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 393 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/010/06010925.pdf [firstpage_image] =>[orig_patent_app_number] => 033521 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/033521
Method of making dual-gate CMOSFET Mar 1, 1998 Issued
09/031683 PROCESS FOR FABRICATING A HIGH PERFORMANCE LOGIC AND EMBEDDED DRAM DEVICES ON A SINGLE SEMICONDUCTOR CHIP Feb 26, 1998 Issued
Array ( [id] => 4084707 [patent_doc_number] => 06025239 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Method for fabricating an electrostatic discharge device' [patent_app_type] => 1 [patent_app_number] => 9/027572 [patent_app_country] => US [patent_app_date] => 1998-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2174 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025239.pdf [firstpage_image] =>[orig_patent_app_number] => 027572 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/027572
Method for fabricating an electrostatic discharge device Feb 22, 1998 Issued
Array ( [id] => 4107481 [patent_doc_number] => 06057199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Method of producing a semiconductor body' [patent_app_type] => 1 [patent_app_number] => 9/022691 [patent_app_country] => US [patent_app_date] => 1998-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3199 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057199.pdf [firstpage_image] =>[orig_patent_app_number] => 022691 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/022691
Method of producing a semiconductor body Feb 11, 1998 Issued
Array ( [id] => 4233521 [patent_doc_number] => 06117778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Semiconductor wafer edge bead removal method and tool' [patent_app_type] => 1 [patent_app_number] => 9/021762 [patent_app_country] => US [patent_app_date] => 1998-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3381 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117778.pdf [firstpage_image] =>[orig_patent_app_number] => 021762 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/021762
Semiconductor wafer edge bead removal method and tool Feb 10, 1998 Issued
Array ( [id] => 1441029 [patent_doc_number] => 06335255 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Manufacturing a heterobipolar transistor and a laser diode on the same substrate' [patent_app_type] => B1 [patent_app_number] => 09/019971 [patent_app_country] => US [patent_app_date] => 1998-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4056 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335255.pdf [firstpage_image] =>[orig_patent_app_number] => 09019971 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/019971
Manufacturing a heterobipolar transistor and a laser diode on the same substrate Feb 5, 1998 Issued
Array ( [id] => 4155186 [patent_doc_number] => 06114208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method for fabricating complementary MOS transistor' [patent_app_type] => 1 [patent_app_number] => 9/007022 [patent_app_country] => US [patent_app_date] => 1998-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3080 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114208.pdf [firstpage_image] =>[orig_patent_app_number] => 007022 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/007022
Method for fabricating complementary MOS transistor Jan 13, 1998 Issued
Array ( [id] => 3944042 [patent_doc_number] => 05998252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method of salicide and sac (self-aligned contact) integration' [patent_app_type] => 1 [patent_app_number] => 8/998630 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 2222 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 412 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998252.pdf [firstpage_image] =>[orig_patent_app_number] => 998630 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998630
Method of salicide and sac (self-aligned contact) integration Dec 28, 1997 Issued
Array ( [id] => 3911254 [patent_doc_number] => 06001723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Application of wire bond loop as integrated circuit package component interconnect' [patent_app_type] => 1 [patent_app_number] => 8/998442 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3969 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/001/06001723.pdf [firstpage_image] =>[orig_patent_app_number] => 998442 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998442
Application of wire bond loop as integrated circuit package component interconnect Dec 23, 1997 Issued
Array ( [id] => 4130484 [patent_doc_number] => 06033984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Dual damascene with bond pads' [patent_app_type] => 1 [patent_app_number] => 8/997682 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4033 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033984.pdf [firstpage_image] =>[orig_patent_app_number] => 997682 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997682
Dual damascene with bond pads Dec 22, 1997 Issued
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