Christy L. Novacek

Array ( [id] => 7170671 [patent_doc_number] => 20050202680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Method for shrinking a dimension of a gate' [patent_app_type] => utility [patent_app_number] => 10/799687 [patent_app_country] => US [patent_app_date] => 2004-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2930 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20050202680.pdf [firstpage_image] =>[orig_patent_app_number] => 10799687 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7349182 [patent_doc_number] => 20040248397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Methods of forming a conductive structure in an integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/796437 [patent_app_country] => US [patent_app_date] => 2004-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3597 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20040248397.pdf [firstpage_image] =>[orig_patent_app_number] => 10796437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7406756 [patent_doc_number] => 20040175917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Metal electrode and bonding method using the metal electrode' [patent_app_type] => new [patent_app_number] => 10/790757 [patent_app_country] => US [patent_app_date] => 2004-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9891 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20040175917.pdf [firstpage_image] =>[orig_patent_app_number] => 10790757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 651257 [patent_doc_number] => 07112834 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-26 [patent_title] => 'Gate etch process' [patent_app_type] => utility [patent_app_number] => 10/791657 [patent_app_country] => US [patent_app_date] => 2004-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3105 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/112/07112834.pdf [firstpage_image] =>[orig_patent_app_number] => 10791657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 641756 [patent_doc_number] => 07122455 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-17 [patent_title] => 'Patterning with rigid organic under-layer' [patent_app_type] => utility [patent_app_number] => 10/790567 [patent_app_country] => US [patent_app_date] => 2004-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3531 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/122/07122455.pdf [firstpage_image] =>[orig_patent_app_number] => 10790567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7104118 [patent_doc_number] => 20050106844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Method of fabricating a MOSFET device' [patent_app_type] => utility [patent_app_number] => 10/788807 [patent_app_country] => US [patent_app_date] => 2004-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2891 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20050106844.pdf [firstpage_image] =>[orig_patent_app_number] => 10788807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 404639 [patent_doc_number] => 07288468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Luminescent efficiency of semiconductor nanocrystals by surface treatment' [patent_app_type] => utility [patent_app_number] => 10/785067 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4436 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288468.pdf [firstpage_image] =>[orig_patent_app_number] => 10785067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7050866 [patent_doc_number] => 20050186753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'FIB exposure of alignment marks in MIM technology' [patent_app_type] => utility [patent_app_number] => 10/786187 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20050186753.pdf [firstpage_image] =>[orig_patent_app_number] => 10786187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 650936 [patent_doc_number] => 07112513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Sub-micron space liner and densification process' [patent_app_type] => utility [patent_app_number] => 10/782997 [patent_app_country] => US [patent_app_date] => 2004-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3525 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/112/07112513.pdf [firstpage_image] =>[orig_patent_app_number] => 10782997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7448654 [patent_doc_number] => 20040164420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Sputtering target compositions, and methods of inhibiting copper diffusion into a substrate' [patent_app_type] => new [patent_app_number] => 10/783247 [patent_app_country] => US [patent_app_date] => 2004-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6935 [patent_no_of_claims] => 170 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20040164420.pdf [firstpage_image] =>[orig_patent_app_number] => 10783247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7349180 [patent_doc_number] => 20040248396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Method for forming multi-layer wiring structure' [patent_app_type] => new [patent_app_number] => 10/782084 [patent_app_country] => US [patent_app_date] => 2004-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4716 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20040248396.pdf [firstpage_image] =>[orig_patent_app_number] => 10782084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 397551 [patent_doc_number] => 07294520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Method for fabricating a plurality of semiconductor bodies, and electronic semiconductor body' [patent_app_type] => utility [patent_app_number] => 10/780317 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4273 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/294/07294520.pdf [firstpage_image] =>[orig_patent_app_number] => 10780317 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7136982 [patent_doc_number] => 20050181630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Method of making a semiconductor device using treated photoresist' [patent_app_type] => utility [patent_app_number] => 10/779007 [patent_app_country] => US [patent_app_date] => 2004-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2542 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20050181630.pdf [firstpage_image] =>[orig_patent_app_number] => 10779007 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7136976 [patent_doc_number] => 20050181624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Method of forming quantum dots at predetermined positions on a substrate' [patent_app_type] => utility [patent_app_number] => 10/779457 [patent_app_country] => US [patent_app_date] => 2004-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3489 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20050181624.pdf [firstpage_image] =>[orig_patent_app_number] => 10779457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7429390 [patent_doc_number] => 20040161919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Methods of forming integrated circuit devices including insulation layers' [patent_app_type] => new [patent_app_number] => 10/775677 [patent_app_country] => US [patent_app_date] => 2004-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8411 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20040161919.pdf [firstpage_image] =>[orig_patent_app_number] => 10775677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6912479 [patent_doc_number] => 20050176237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'In-situ liner formation during reactive ion etch' [patent_app_type] => utility [patent_app_number] => 10/772777 [patent_app_country] => US [patent_app_date] => 2004-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2125 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20050176237.pdf [firstpage_image] =>[orig_patent_app_number] => 10772777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7673256 [patent_doc_number] => 20040180523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Method for making a semiconductor device having a high-k gate dielectric' [patent_app_type] => new [patent_app_number] => 10/771267 [patent_app_country] => US [patent_app_date] => 2004-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2565 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20040180523.pdf [firstpage_image] =>[orig_patent_app_number] => 10771267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7005325 [patent_doc_number] => 20050170638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Method for forming dual damascene interconnect structure' [patent_app_type] => utility [patent_app_number] => 10/768217 [patent_app_country] => US [patent_app_date] => 2004-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3156 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20050170638.pdf [firstpage_image] =>[orig_patent_app_number] => 10768217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7005293 [patent_doc_number] => 20050170606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Method of achieving improved STI gap fill with reduced stress' [patent_app_type] => utility [patent_app_number] => 10/767657 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3926 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20050170606.pdf [firstpage_image] =>[orig_patent_app_number] => 10767657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 724512 [patent_doc_number] => 07045461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Metal plating method, pretreatment agent, and semiconductor wafer and semiconductor device obtained using these' [patent_app_type] => utility [patent_app_number] => 10/767697 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 5661 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/045/07045461.pdf [firstpage_image] =>[orig_patent_app_number] => 10767697 [rel_patent_id] =>[rel_patent_doc_number] =>)