Christy L. Novacek

Array ( [id] => 1063656 [patent_doc_number] => 06849899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'High speed trench DMOS' [patent_app_type] => utility [patent_app_number] => 10/673887 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3652 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/849/06849899.pdf [firstpage_image] =>[orig_patent_app_number] => 10673887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1110822 [patent_doc_number] => 06806104 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Method for detecting defect of semiconductor device' [patent_app_type] => B1 [patent_app_number] => 10/605357 [patent_app_country] => US [patent_app_date] => 2003-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2297 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806104.pdf [firstpage_image] =>[orig_patent_app_number] => 10605357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1069228 [patent_doc_number] => 06844610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-18 [patent_title] => 'Integrated circuit devices including a resistor pattern' [patent_app_type] => utility [patent_app_number] => 10/672497 [patent_app_country] => US [patent_app_date] => 2003-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5616 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/844/06844610.pdf [firstpage_image] =>[orig_patent_app_number] => 10672497 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1024515 [patent_doc_number] => 06884667 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-26 [patent_title] => 'Field effect transistor with stressed channel and method for making same' [patent_app_type] => utility [patent_app_number] => 10/669727 [patent_app_country] => US [patent_app_date] => 2003-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 25 [patent_no_of_words] => 3051 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/884/06884667.pdf [firstpage_image] =>[orig_patent_app_number] => 10669727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 540137 [patent_doc_number] => 07176563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Electronically grounded heat spreader' [patent_app_type] => utility [patent_app_number] => 10/665997 [patent_app_country] => US [patent_app_date] => 2003-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2609 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/176/07176563.pdf [firstpage_image] =>[orig_patent_app_number] => 10665997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 739027 [patent_doc_number] => 07034400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Dual damascene interconnect structure using low stress fluorosilicate insulator with copper conductors' [patent_app_type] => utility [patent_app_number] => 10/659778 [patent_app_country] => US [patent_app_date] => 2003-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2529 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/034/07034400.pdf [firstpage_image] =>[orig_patent_app_number] => 10659778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 757632 [patent_doc_number] => 07015094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Method of fabricating a ferromagnetic memory device' [patent_app_type] => utility [patent_app_number] => 10/654717 [patent_app_country] => US [patent_app_date] => 2003-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4701 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/015/07015094.pdf [firstpage_image] =>[orig_patent_app_number] => 10654717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 968528 [patent_doc_number] => 06939802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/650677 [patent_app_country] => US [patent_app_date] => 2003-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 3779 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/939/06939802.pdf [firstpage_image] =>[orig_patent_app_number] => 10650677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 963612 [patent_doc_number] => 06949424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-27 [patent_title] => 'Single poly-emitter PNP using DWELL diffusion in a BiCMOS technology' [patent_app_type] => utility [patent_app_number] => 10/650621 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 7548 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/949/06949424.pdf [firstpage_image] =>[orig_patent_app_number] => 10650621 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7423321 [patent_doc_number] => 20040229401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Method for fabricating semiconductor component having stacked, encapsulated dice' [patent_app_type] => new [patent_app_number] => 10/649147 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5677 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20040229401.pdf [firstpage_image] =>[orig_patent_app_number] => 10649147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7083319 [patent_doc_number] => 20050048699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Method and system for integrated circuit packaging' [patent_app_type] => utility [patent_app_number] => 10/648987 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20050048699.pdf [firstpage_image] =>[orig_patent_app_number] => 10648987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1040561 [patent_doc_number] => 06869859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/647427 [patent_app_country] => US [patent_app_date] => 2003-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 62 [patent_no_of_words] => 9536 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/869/06869859.pdf [firstpage_image] =>[orig_patent_app_number] => 10647427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7443248 [patent_doc_number] => 20040185678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Integrated circuit dielectric and method' [patent_app_type] => new [patent_app_number] => 10/645387 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 5455 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20040185678.pdf [firstpage_image] =>[orig_patent_app_number] => 10645387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5694298 [patent_doc_number] => 20060154445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Method for manufacturing soi wafer' [patent_app_type] => utility [patent_app_number] => 10/525397 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6340 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20060154445.pdf [firstpage_image] =>[orig_patent_app_number] => 10525397 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 963582 [patent_doc_number] => 06949394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-27 [patent_title] => 'Optical semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/645437 [patent_app_country] => US [patent_app_date] => 2003-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 71 [patent_no_of_words] => 12451 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/949/06949394.pdf [firstpage_image] =>[orig_patent_app_number] => 10645437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7465505 [patent_doc_number] => 20040053495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Method of forming barrier layers' [patent_app_type] => new [patent_app_number] => 10/642607 [patent_app_country] => US [patent_app_date] => 2003-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5424 [patent_no_of_claims] => 91 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20040053495.pdf [firstpage_image] =>[orig_patent_app_number] => 10642607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7203994 [patent_doc_number] => 20050042851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Connector terminal device and its fabrication method' [patent_app_type] => utility [patent_app_number] => 10/642637 [patent_app_country] => US [patent_app_date] => 2003-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1319 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20050042851.pdf [firstpage_image] =>[orig_patent_app_number] => 10642637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7395229 [patent_doc_number] => 20040038508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Method for fabricating a semiconductor device having a tapered-mesa side-wall film' [patent_app_type] => new [patent_app_number] => 10/642667 [patent_app_country] => US [patent_app_date] => 2003-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3179 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20040038508.pdf [firstpage_image] =>[orig_patent_app_number] => 10642667 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6969641 [patent_doc_number] => 20050035351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Device and method for protecting gate terminal and lead' [patent_app_type] => utility [patent_app_number] => 10/642417 [patent_app_country] => US [patent_app_date] => 2003-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3648 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20050035351.pdf [firstpage_image] =>[orig_patent_app_number] => 10642417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6971886 [patent_doc_number] => 20050037596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Internal gettering in SIMOX SOI silicon substrates' [patent_app_type] => utility [patent_app_number] => 10/640917 [patent_app_country] => US [patent_app_date] => 2003-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6106 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20050037596.pdf [firstpage_image] =>[orig_patent_app_number] => 10640917 [rel_patent_id] =>[rel_patent_doc_number] =>)