
Christy L. Novacek
Examiner (ID: 13644)
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822 |
| Total Applications | 465 |
| Issued Applications | 357 |
| Pending Applications | 12 |
| Abandoned Applications | 96 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7269964
[patent_doc_number] => 20040058482
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-25
[patent_title] => 'Method for improving a semiconductor substrate having SiGe film and semiconductor device manufactured by using this method'
[patent_app_type] => new
[patent_app_number] => 10/639647
[patent_app_country] => US
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[pdf_file] => publications/A1/0058/20040058482.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/639647 | Method for improving a semiconductor substrate having SiGe film and semiconductor device manufactured by using this method | Aug 12, 2003 | Issued |
Array
(
[id] => 7620073
[patent_doc_number] => 06943110
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-09-13
[patent_title] => 'Wafer processing apparatus and methods for depositing cobalt silicide'
[patent_app_type] => utility
[patent_app_number] => 10/640779
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[patent_app_date] => 2003-08-13
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Array
(
[id] => 701411
[patent_doc_number] => 07063992
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[patent_kind] => B2
[patent_issue_date] => 2006-06-20
[patent_title] => 'Semiconductor substrate surface preparation using high temperature convection heating'
[patent_app_type] => utility
[patent_app_number] => 10/637447
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/637447 | Semiconductor substrate surface preparation using high temperature convection heating | Aug 7, 2003 | Issued |
Array
(
[id] => 7154788
[patent_doc_number] => 20050026409
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-03
[patent_title] => 'Method for forming DRAM cell bit line and bit line contact structure'
[patent_app_type] => utility
[patent_app_number] => 10/628507
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[patent_app_date] => 2003-07-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/628507 | Method for forming DRAM cell bit line and bit line contact structure | Jul 28, 2003 | Issued |
Array
(
[id] => 7287305
[patent_doc_number] => 20040147101
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-29
[patent_title] => 'Surface preparation prior to deposition'
[patent_app_type] => new
[patent_app_number] => 10/626217
[patent_app_country] => US
[patent_app_date] => 2003-07-24
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[firstpage_image] =>[orig_patent_app_number] => 10626217
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/626217 | Surface preparation prior to deposition | Jul 23, 2003 | Issued |
Array
(
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[patent_doc_number] => 20040137663
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[patent_issue_date] => 2004-07-15
[patent_title] => 'Method of reducing internal stress in materials'
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[pdf_file] => publications/A1/0137/20040137663.pdf
[firstpage_image] =>[orig_patent_app_number] => 10624427
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/624427 | Method of reducing internal stress in materials | Jul 21, 2003 | Issued |
Array
(
[id] => 715360
[patent_doc_number] => 07052922
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[patent_issue_date] => 2006-05-30
[patent_title] => 'Stable electroless fine pitch interconnect plating'
[patent_app_type] => utility
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[patent_app_country] => US
[patent_app_date] => 2003-07-21
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[pdf_file] => patents/07/052/07052922.pdf
[firstpage_image] =>[orig_patent_app_number] => 10622497
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/622497 | Stable electroless fine pitch interconnect plating | Jul 20, 2003 | Issued |
Array
(
[id] => 7675159
[patent_doc_number] => 20040126959
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[patent_issue_date] => 2004-07-01
[patent_title] => 'Method of manufacturing ferroelectric memory device'
[patent_app_type] => new
[patent_app_number] => 10/620927
[patent_app_country] => US
[patent_app_date] => 2003-07-16
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[pdf_file] => publications/A1/0126/20040126959.pdf
[firstpage_image] =>[orig_patent_app_number] => 10620927
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/620927 | Method of manufacturing ferroelectric memory device | Jul 15, 2003 | Issued |
Array
(
[id] => 1005329
[patent_doc_number] => 06905923
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-06-14
[patent_title] => 'Offset spacer process for forming N-type transistors'
[patent_app_type] => utility
[patent_app_number] => 10/619877
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[pdf_file] => patents/06/905/06905923.pdf
[firstpage_image] =>[orig_patent_app_number] => 10619877
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/619877 | Offset spacer process for forming N-type transistors | Jul 14, 2003 | Issued |
Array
(
[id] => 7399159
[patent_doc_number] => 20040018747
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-29
[patent_title] => 'Deposition method of a dielectric layer'
[patent_app_type] => new
[patent_app_number] => 10/617767
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[patent_app_date] => 2003-07-14
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[pdf_file] => publications/A1/0018/20040018747.pdf
[firstpage_image] =>[orig_patent_app_number] => 10617767
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/617767 | Deposition method of a dielectric layer | Jul 13, 2003 | Issued |
Array
(
[id] => 7089122
[patent_doc_number] => 20050009235
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[patent_issue_date] => 2005-01-13
[patent_title] => 'Method of forming a scribe line on a ceramic substrate'
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[firstpage_image] =>[orig_patent_app_number] => 10618377
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/618377 | Method of forming a scribe line on a ceramic substrate | Jul 10, 2003 | Issued |
Array
(
[id] => 7203705
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[patent_title] => 'Capacitor fabrication methods and capacitor structures including niobium oxide'
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Array
(
[id] => 1050036
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[patent_title] => 'Semiconductor memory device and fabrication method thereof using damascene bitline process'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/607597 | Semiconductor memory device and fabrication method thereof using damascene bitline process | Jun 26, 2003 | Issued |
Array
(
[id] => 7312648
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/603077 | Method of manufacturing semiconductor device and method of forming pattern | Jun 24, 2003 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/601037 | Method to fabricate dual metal CMOS devices | Jun 18, 2003 | Issued |
Array
(
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[patent_title] => 'Gate dielectric quality for replacement metal gate transistors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/462667 | Gate dielectric quality for replacement metal gate transistors | Jun 16, 2003 | Issued |
Array
(
[id] => 1113695
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[patent_title] => 'Light emitting diode used as an illuminant of an image sensor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/457317 | Light emitting diode used as an illuminant of an image sensor | Jun 9, 2003 | Issued |
Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/442449 | Method for fabricating a self-aligned bipolar transistor having increased manufacturability and related structure | May 20, 2003 | Issued |