
Christy L. Novacek
Examiner (ID: 13644)
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822 |
| Total Applications | 465 |
| Issued Applications | 357 |
| Pending Applications | 12 |
| Abandoned Applications | 96 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 931083
[patent_doc_number] => 06979587
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-12-27
[patent_title] => 'Image sensor and method for fabricating the same'
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[patent_app_number] => 10/330287
[patent_app_country] => US
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[pdf_file] => patents/06/979/06979587.pdf
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Array
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[patent_doc_number] => 06815334
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[patent_issue_date] => 2004-11-09
[patent_title] => 'Method for forming multi-layer metal line of semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/330057 | Method for forming multi-layer metal line of semiconductor device | Dec 29, 2002 | Issued |
Array
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Array
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Array
(
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[patent_doc_number] => RE038914
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[patent_kind] => E1
[patent_issue_date] => 2005-12-06
[patent_title] => 'Dual damascene patterned conductor layer formation method without etch stop layer'
[patent_app_type] => reissue
[patent_app_number] => 10/329863
[patent_app_country] => US
[patent_app_date] => 2002-12-26
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[pdf_file] => patents/RE/038/RE038914.pdf
[firstpage_image] =>[orig_patent_app_number] => 10329863
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/329863 | Dual damascene patterned conductor layer formation method without etch stop layer | Dec 25, 2002 | Issued |
Array
(
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[patent_doc_number] => 06949441
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[patent_issue_date] => 2005-09-27
[patent_title] => 'Ferroelectric memory device and method of making the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/325838 | Ferroelectric memory device and method of making the same | Dec 22, 2002 | Issued |
Array
(
[id] => 1137992
[patent_doc_number] => 06780664
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[patent_issue_date] => 2004-08-24
[patent_title] => 'Nanotube tip for atomic force microscope'
[patent_app_type] => B1
[patent_app_number] => 10/324327
[patent_app_country] => US
[patent_app_date] => 2002-12-20
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[pdf_file] => patents/06/780/06780664.pdf
[firstpage_image] =>[orig_patent_app_number] => 10324327
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/324327 | Nanotube tip for atomic force microscope | Dec 19, 2002 | Issued |
Array
(
[id] => 1027972
[patent_doc_number] => 06881688
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[patent_issue_date] => 2005-04-19
[patent_title] => 'Method of fabricating a vertically profiled electrode and semiconductor device comprising such an electrode'
[patent_app_type] => utility
[patent_app_number] => 10/323817
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[patent_app_date] => 2002-12-20
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[pdf_file] => patents/06/881/06881688.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/323817 | Method of fabricating a vertically profiled electrode and semiconductor device comprising such an electrode | Dec 19, 2002 | Issued |
Array
(
[id] => 760793
[patent_doc_number] => 07011983
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[patent_issue_date] => 2006-03-14
[patent_title] => 'Large organic devices and methods of fabricating large organic devices'
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Array
(
[id] => 1059522
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[patent_title] => 'Semiconductor device and method for fabricating the same'
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Array
(
[id] => 1146238
[patent_doc_number] => 06773975
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[patent_title] => 'Formation of a shallow trench isolation structure in integrated circuits'
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Array
(
[id] => 1146535
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[patent_title] => 'Strained silicon-on-insulator (SSOI) and method to form the same'
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Array
(
[id] => 6856304
[patent_doc_number] => 20030129805
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[patent_title] => 'Methods of forming MIM type capacitors by forming upper and lower electrode layers in a recess that exposes a source/drain region of a transistor and MIM capacitors so formed'
[patent_app_type] => new
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Array
(
[id] => 6847148
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[patent_title] => 'Method of manufacturing a thin film transistor'
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Array
(
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[patent_title] => 'High density modularity for IC\'s'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/289549 | High-density modularity for ICS | Nov 5, 2002 | Issued |
Array
(
[id] => 1101736
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[patent_title] => 'Method for forming integrated dielectric layers'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/284517 | Method for forming integrated dielectric layers | Oct 29, 2002 | Issued |
Array
(
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[patent_title] => 'Ultra-violet treatment for a tunnel barrier layer in a tunnel junction device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/282577 | Ultra-violet treatment for a tunnel barrier layer in a tunnel junction device | Oct 28, 2002 | Abandoned |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/281127 | Contact structure a semiconductor device and manufacturing method thereof | Oct 27, 2002 | Issued |
| 10/274777 | Film stack having a silicon germanium layer and a thin amorphous seed layer | Oct 17, 2002 | Abandoned |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/272757 | Technique for growing single crystal material on top of an insulator | Oct 16, 2002 | Abandoned |