
Christy L. Novacek
Examiner (ID: 13644)
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822 |
| Total Applications | 465 |
| Issued Applications | 357 |
| Pending Applications | 12 |
| Abandoned Applications | 96 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1314579
[patent_doc_number] => 06614119
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-02
[patent_title] => 'Semiconductor device and method of fabricating the same'
[patent_app_type] => B1
[patent_app_number] => 09/521771
[patent_app_country] => US
[patent_app_date] => 2000-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 10025
[patent_no_of_claims] => 11
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[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/614/06614119.pdf
[firstpage_image] =>[orig_patent_app_number] => 09521771
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/521771 | Semiconductor device and method of fabricating the same | Mar 8, 2000 | Issued |
Array
(
[id] => 7643925
[patent_doc_number] => 06429113
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Method for connecting an electrical device to a circuit substrate'
[patent_app_type] => B1
[patent_app_number] => 09/518447
[patent_app_country] => US
[patent_app_date] => 2000-03-03
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/429/06429113.pdf
[firstpage_image] =>[orig_patent_app_number] => 09518447
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/518447 | Method for connecting an electrical device to a circuit substrate | Mar 2, 2000 | Issued |
Array
(
[id] => 1196685
[patent_doc_number] => 06727161
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-27
[patent_title] => 'Isolation technology for submicron semiconductor devices'
[patent_app_type] => B2
[patent_app_number] => 09/505737
[patent_app_country] => US
[patent_app_date] => 2000-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/727/06727161.pdf
[firstpage_image] =>[orig_patent_app_number] => 09505737
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/505737 | Isolation technology for submicron semiconductor devices | Feb 15, 2000 | Issued |
Array
(
[id] => 1552963
[patent_doc_number] => 06400002
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-04
[patent_title] => 'Methods of forming field effect transistors and related field effect transistor constructions'
[patent_app_type] => B1
[patent_app_number] => 09/490257
[patent_app_country] => US
[patent_app_date] => 2000-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/400/06400002.pdf
[firstpage_image] =>[orig_patent_app_number] => 09490257
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/490257 | Methods of forming field effect transistors and related field effect transistor constructions | Jan 23, 2000 | Issued |
Array
(
[id] => 1565526
[patent_doc_number] => 06376263
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-23
[patent_title] => 'Non-destructive module placement verification'
[patent_app_type] => B1
[patent_app_number] => 09/489897
[patent_app_country] => US
[patent_app_date] => 2000-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/06/376/06376263.pdf
[firstpage_image] =>[orig_patent_app_number] => 09489897
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/489897 | Non-destructive module placement verification | Jan 23, 2000 | Issued |
Array
(
[id] => 6985600
[patent_doc_number] => 20010035570
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-01
[patent_title] => 'Package for semiconductor devices'
[patent_app_type] => new
[patent_app_number] => 09/488087
[patent_app_country] => US
[patent_app_date] => 2000-01-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0035/20010035570.pdf
[firstpage_image] =>[orig_patent_app_number] => 09488087
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/488087 | Build-up board package for semiconductor devices | Jan 19, 2000 | Issued |
Array
(
[id] => 6130181
[patent_doc_number] => 20020076917
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-20
[patent_title] => 'DUAL DAMASCENE INTERCONNECT STRUCTURE USING LOW STRESS FLOUROSILICATE INSULATOR WITH COPPER CONDUCTORS'
[patent_app_type] => new
[patent_app_number] => 09/467207
[patent_app_country] => US
[patent_app_date] => 1999-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2430
[patent_no_of_claims] => 19
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0076/20020076917.pdf
[firstpage_image] =>[orig_patent_app_number] => 09467207
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/467207 | DUAL DAMASCENE INTERCONNECT STRUCTURE USING LOW STRESS FLOUROSILICATE INSULATOR WITH COPPER CONDUCTORS | Dec 19, 1999 | Abandoned |
Array
(
[id] => 1375834
[patent_doc_number] => 06559020
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-06
[patent_title] => 'Bipolar device with silicon germanium (SiGe) base region'
[patent_app_type] => B1
[patent_app_number] => 09/421957
[patent_app_country] => US
[patent_app_date] => 1999-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 3259
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[pdf_file] => patents/06/559/06559020.pdf
[firstpage_image] =>[orig_patent_app_number] => 09421957
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/421957 | Bipolar device with silicon germanium (SiGe) base region | Oct 19, 1999 | Issued |
Array
(
[id] => 1249082
[patent_doc_number] => 06674105
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-01-06
[patent_title] => 'Semiconductor memory device and method of forming the same'
[patent_app_type] => B2
[patent_app_number] => 09/419307
[patent_app_country] => US
[patent_app_date] => 1999-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[pdf_file] => patents/06/674/06674105.pdf
[firstpage_image] =>[orig_patent_app_number] => 09419307
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/419307 | Semiconductor memory device and method of forming the same | Oct 17, 1999 | Issued |
Array
(
[id] => 1466917
[patent_doc_number] => 06458627
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-01
[patent_title] => 'Semiconductor chip package and method of fabricating same'
[patent_app_type] => B1
[patent_app_number] => 09/415267
[patent_app_country] => US
[patent_app_date] => 1999-10-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/458/06458627.pdf
[firstpage_image] =>[orig_patent_app_number] => 09415267
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/415267 | Semiconductor chip package and method of fabricating same | Oct 11, 1999 | Issued |
Array
(
[id] => 6711220
[patent_doc_number] => 20030170969
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-11
[patent_title] => 'SEMICONDUCTOR PROCESSING EMPLOYING A SEMICONDUCTING SPACER'
[patent_app_type] => new
[patent_app_number] => 09/401797
[patent_app_country] => US
[patent_app_date] => 1999-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0170/20030170969.pdf
[firstpage_image] =>[orig_patent_app_number] => 09401797
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/401797 | Semiconductor processing employing a semiconductor spacer | Sep 21, 1999 | Issued |
Array
(
[id] => 1494900
[patent_doc_number] => 06403433
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-11
[patent_title] => 'Source/drain doping technique for ultra-thin-body SOI MOS transistors'
[patent_app_type] => B1
[patent_app_number] => 09/397217
[patent_app_country] => US
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[pdf_file] => patents/06/403/06403433.pdf
[firstpage_image] =>[orig_patent_app_number] => 09397217
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/397217 | Source/drain doping technique for ultra-thin-body SOI MOS transistors | Sep 15, 1999 | Issued |
Array
(
[id] => 1188890
[patent_doc_number] => 06734121
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[patent_kind] => B2
[patent_issue_date] => 2004-05-11
[patent_title] => 'Methods of treating surfaces of substrates'
[patent_app_type] => B2
[patent_app_number] => 09/389290
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[pdf_file] => patents/06/734/06734121.pdf
[firstpage_image] =>[orig_patent_app_number] => 09389290
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/389290 | Methods of treating surfaces of substrates | Sep 1, 1999 | Issued |
Array
(
[id] => 1068742
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[patent_issue_date] => 2005-01-18
[patent_title] => 'Method for fabricating a semiconductor storage device having an increased dielectric film area'
[patent_app_type] => utility
[patent_app_number] => 09/387857
[patent_app_country] => US
[patent_app_date] => 1999-09-01
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[firstpage_image] =>[orig_patent_app_number] => 09387857
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/387857 | Method for fabricating a semiconductor storage device having an increased dielectric film area | Aug 31, 1999 | Issued |
Array
(
[id] => 1378684
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[patent_country] => US
[patent_kind] => B1
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[patent_title] => 'Semiconductor device and process for producing semiconductor device'
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[firstpage_image] =>[orig_patent_app_number] => 09384647
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/384647 | Semiconductor device and process for producing semiconductor device | Aug 26, 1999 | Issued |
Array
(
[id] => 5870717
[patent_doc_number] => 20020047208
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[patent_kind] => A1
[patent_issue_date] => 2002-04-25
[patent_title] => 'METHOD AND STRUCTURE FOR IMPROVING ELECTROMIGRATION OF CHIP INTERCONNECTS'
[patent_app_type] => new
[patent_app_number] => 09/377337
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 09377337
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/377337 | Method and structure for improving electromigration of chip interconnects | Aug 17, 1999 | Issued |
Array
(
[id] => 6897481
[patent_doc_number] => 20010045646
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-29
[patent_title] => 'SILICON OXYNITRIDE ARC FOR METAL PATTERNING'
[patent_app_type] => new
[patent_app_number] => 09/371920
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/371920 | SILICON OXYNITRIDE ARC FOR METAL PATTERNING | Aug 10, 1999 | Abandoned |
Array
(
[id] => 1574872
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[patent_issue_date] => 2002-10-22
[patent_title] => 'Manufacture method and system for semiconductor device with thin gate insulating film of oxynitride'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/342057 | Manufacture method and system for semiconductor device with thin gate insulating film of oxynitride | Jun 28, 1999 | Issued |
Array
(
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[patent_title] => 'Low temperature self-aligned collar formation'
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[patent_app_number] => 09/324927
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[firstpage_image] =>[orig_patent_app_number] => 09324927
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/324927 | Low temperature self-aligned collar formation | Jun 2, 1999 | Issued |
Array
(
[id] => 4327487
[patent_doc_number] => 06319828
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[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Method for manufacturing a chip scale package having copper traces selectively plated with gold'
[patent_app_type] => 1
[patent_app_number] => 9/317537
[patent_app_country] => US
[patent_app_date] => 1999-05-24
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[pdf_file] => patents/06/319/06319828.pdf
[firstpage_image] =>[orig_patent_app_number] => 317537
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/317537 | Method for manufacturing a chip scale package having copper traces selectively plated with gold | May 23, 1999 | Issued |