Search

Christy L. Novacek

Examiner (ID: 17383)

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
465
Issued Applications
357
Pending Applications
12
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9924680 [patent_doc_number] => 08982654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'DRAM sub-array level refresh' [patent_app_type] => utility [patent_app_number] => 14/088098 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14088098 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/088098
DRAM sub-array level refresh Nov 21, 2013 Issued
Array ( [id] => 11095619 [patent_doc_number] => 20160292588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'A METHOD AND AN APPARATUS FOR EFFICIENT DATA PROCESSING' [patent_app_type] => utility [patent_app_number] => 15/038453 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1514 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15038453 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/038453
A METHOD AND AN APPARATUS FOR EFFICIENT DATA PROCESSING Nov 21, 2013 Abandoned
Array ( [id] => 9669474 [patent_doc_number] => 20140233337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/087444 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9444 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087444 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/087444
Nonvolatile memory device and memory system including the same Nov 21, 2013 Issued
Array ( [id] => 9819378 [patent_doc_number] => 08929173 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-06 [patent_title] => 'Data strobe control device' [patent_app_type] => utility [patent_app_number] => 14/085930 [patent_app_country] => US [patent_app_date] => 2013-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5937 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14085930 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/085930
Data strobe control device Nov 20, 2013 Issued
Array ( [id] => 10899855 [patent_doc_number] => 08923084 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-30 [patent_title] => 'Memory and memory system including the same' [patent_app_type] => utility [patent_app_number] => 14/086506 [patent_app_country] => US [patent_app_date] => 2013-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8494 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14086506 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/086506
Memory and memory system including the same Nov 20, 2013 Issued
Array ( [id] => 9733426 [patent_doc_number] => 20140269135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'CIRCUIT AND SYSTEM FOR CONCURRENTLY PROGRAMMING MULTIPLE BITS OF OTP MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 14/085228 [patent_app_country] => US [patent_app_date] => 2013-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5852 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14085228 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/085228
Circuit and system for concurrently programming multiple bits of OTP memory devices Nov 19, 2013 Issued
Array ( [id] => 9877159 [patent_doc_number] => 08964440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Stacked semiconductor devices including a master device' [patent_app_type] => utility [patent_app_number] => 14/082454 [patent_app_country] => US [patent_app_date] => 2013-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 4013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082454 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/082454
Stacked semiconductor devices including a master device Nov 17, 2013 Issued
Array ( [id] => 9470737 [patent_doc_number] => 08724380 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-13 [patent_title] => 'Method for reading and writing multi-level cells' [patent_app_type] => utility [patent_app_number] => 14/079518 [patent_app_country] => US [patent_app_date] => 2013-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 7348 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14079518 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/079518
Method for reading and writing multi-level cells Nov 12, 2013 Issued
Array ( [id] => 10893934 [patent_doc_number] => 08917560 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-23 [patent_title] => 'Half bit line high level voltage genertor, memory device and driving method' [patent_app_type] => utility [patent_app_number] => 14/079613 [patent_app_country] => US [patent_app_date] => 2013-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4567 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14079613 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/079613
Half bit line high level voltage genertor, memory device and driving method Nov 12, 2013 Issued
Array ( [id] => 9870457 [patent_doc_number] => 08958237 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-02-17 [patent_title] => 'Static random access memory timing tracking circuit' [patent_app_type] => utility [patent_app_number] => 14/078895 [patent_app_country] => US [patent_app_date] => 2013-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14078895 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/078895
Static random access memory timing tracking circuit Nov 12, 2013 Issued
Array ( [id] => 9819335 [patent_doc_number] => 08929130 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-06 [patent_title] => 'Two-port SRAM cell structure' [patent_app_type] => utility [patent_app_number] => 14/077314 [patent_app_country] => US [patent_app_date] => 2013-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14077314 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/077314
Two-port SRAM cell structure Nov 11, 2013 Issued
Array ( [id] => 10408129 [patent_doc_number] => 20150293138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'METHOD TO DETERMINE A DIRECTION AND AMPLITUDE OF A CURRENT VELOCITY ESTIMATE OF A MOVING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/440149 [patent_app_country] => US [patent_app_date] => 2013-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6198 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14440149 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/440149
METHOD TO DETERMINE A DIRECTION AND AMPLITUDE OF A CURRENT VELOCITY ESTIMATE OF A MOVING DEVICE Nov 6, 2013 Abandoned
Array ( [id] => 10391437 [patent_doc_number] => 20150276443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'DEVICE AND METHOD FOR ESTIMATING A FLOW OF GAS IN AN ENCLOSURE MAINTAINED AT REDUCED PRESSURE IN RELATION TO THE GAS' [patent_app_type] => utility [patent_app_number] => 14/440264 [patent_app_country] => US [patent_app_date] => 2013-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14712 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14440264 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/440264
Device and method for estimating a flow of gas in an enclosure maintained at reduced pressure in relation to the gas Nov 5, 2013 Issued
Array ( [id] => 9664060 [patent_doc_number] => 08811057 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-19 [patent_title] => 'Power reduction circuit and method' [patent_app_type] => utility [patent_app_number] => 14/051946 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5454 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14051946 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/051946
Power reduction circuit and method Oct 10, 2013 Issued
Array ( [id] => 9959597 [patent_doc_number] => 09007811 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-04-14 [patent_title] => 'Word line driver circuit' [patent_app_type] => utility [patent_app_number] => 14/051762 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6115 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14051762 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/051762
Word line driver circuit Oct 10, 2013 Issued
Array ( [id] => 9516846 [patent_doc_number] => 20140153338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'MEMORY SYSTEM AND METHOD OF OPERATING MEMORY SYSTEM USING SOFT READ VOLTAGES' [patent_app_type] => utility [patent_app_number] => 14/050430 [patent_app_country] => US [patent_app_date] => 2013-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14050430 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/050430
Memory system and method of operating memory system using soft read voltages Oct 9, 2013 Issued
Array ( [id] => 9824793 [patent_doc_number] => 08934285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-13 [patent_title] => 'Method and apparatus for forming a contact in a cell of a resistive random access memory to reduce a voltage required to program the cell' [patent_app_type] => utility [patent_app_number] => 14/050720 [patent_app_country] => US [patent_app_date] => 2013-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14050720 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/050720
Method and apparatus for forming a contact in a cell of a resistive random access memory to reduce a voltage required to program the cell Oct 9, 2013 Issued
Array ( [id] => 10003847 [patent_doc_number] => 09047945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'Systems and methods for reading resistive random access memory (RRAM) cells' [patent_app_type] => utility [patent_app_number] => 14/050678 [patent_app_country] => US [patent_app_date] => 2013-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 7019 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14050678 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/050678
Systems and methods for reading resistive random access memory (RRAM) cells Oct 9, 2013 Issued
Array ( [id] => 9945881 [patent_doc_number] => 08995198 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-31 [patent_title] => 'Multi-pass soft programming' [patent_app_type] => utility [patent_app_number] => 14/050490 [patent_app_country] => US [patent_app_date] => 2013-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14050490 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/050490
Multi-pass soft programming Oct 9, 2013 Issued
Array ( [id] => 9997548 [patent_doc_number] => 09042159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-26 [patent_title] => 'Configuring resistive random access memory (RRAM) array for write operations' [patent_app_type] => utility [patent_app_number] => 14/050696 [patent_app_country] => US [patent_app_date] => 2013-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6853 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14050696 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/050696
Configuring resistive random access memory (RRAM) array for write operations Oct 9, 2013 Issued
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