Search

Christy L. Novacek

Examiner (ID: 17383)

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
465
Issued Applications
357
Pending Applications
12
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8743871 [patent_doc_number] => 20130083588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'MEMORY ELEMENT AND SIGNAL PROCESSING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/608512 [patent_app_country] => US [patent_app_date] => 2012-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13859 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13608512 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/608512
Memory element and signal processing circuit Sep 9, 2012 Issued
Array ( [id] => 8827616 [patent_doc_number] => 20130128661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'MEMORY AND METHOD FOR OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/607900 [patent_app_country] => US [patent_app_date] => 2012-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11860 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13607900 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/607900
Memory and method for operating the same Sep 9, 2012 Issued
Array ( [id] => 9505289 [patent_doc_number] => 08743613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Timing control in synchronous memory data transfer' [patent_app_type] => utility [patent_app_number] => 13/607810 [patent_app_country] => US [patent_app_date] => 2012-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3721 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13607810 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/607810
Timing control in synchronous memory data transfer Sep 9, 2012 Issued
Array ( [id] => 9664092 [patent_doc_number] => 08811088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Method of reading memory cells with different threshold voltages without variation of word line voltage and nonvolatile memory device using the same' [patent_app_type] => utility [patent_app_number] => 13/608030 [patent_app_country] => US [patent_app_date] => 2012-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 14695 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13608030 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/608030
Method of reading memory cells with different threshold voltages without variation of word line voltage and nonvolatile memory device using the same Sep 9, 2012 Issued
Array ( [id] => 10877898 [patent_doc_number] => 08902691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-02 [patent_title] => 'Semiconductor device having charge pump circuit and information processing apparatus including the same' [patent_app_type] => utility [patent_app_number] => 13/607146 [patent_app_country] => US [patent_app_date] => 2012-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5214 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13607146 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/607146
Semiconductor device having charge pump circuit and information processing apparatus including the same Sep 6, 2012 Issued
Array ( [id] => 8588533 [patent_doc_number] => 20130007353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'CONTROL METHOD OF NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/607038 [patent_app_country] => US [patent_app_date] => 2012-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 74 [patent_figures_cnt] => 74 [patent_no_of_words] => 42978 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13607038 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/607038
Control method of nonvolatile memory device Sep 6, 2012 Issued
Array ( [id] => 9052989 [patent_doc_number] => 20130250703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'OUTPUT DRIVER CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/607090 [patent_app_country] => US [patent_app_date] => 2012-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8607 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13607090 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/607090
Output driver circuit and semiconductor storage device Sep 6, 2012 Issued
Array ( [id] => 8890141 [patent_doc_number] => 20130163325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'NON-VOLATILE MEMORY DEVICE, METHOD FOR FABRICATING THE SAME, AND METHOD FOR OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/606818 [patent_app_country] => US [patent_app_date] => 2012-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7000 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13606818 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/606818
Non-volatile memory device, method for fabricating the same, and method for operating the same Sep 6, 2012 Issued
Array ( [id] => 8743869 [patent_doc_number] => 20130083586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'INTEGRATED CIRCUIT WITH A SELF-PROGRAMMED IDENTIFICATION KEY' [patent_app_type] => utility [patent_app_number] => 13/607578 [patent_app_country] => US [patent_app_date] => 2012-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13607578 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/607578
Integrated circuit with a self-programmed identification key Sep 6, 2012 Issued
Array ( [id] => 8949089 [patent_doc_number] => 20130194869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/605942 [patent_app_country] => US [patent_app_date] => 2012-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8810 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13605942 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/605942
Three-dimensional non-volatile memory device Sep 5, 2012 Issued
Array ( [id] => 8790670 [patent_doc_number] => 20130107639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/605854 [patent_app_country] => US [patent_app_date] => 2012-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6138 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13605854 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/605854
Semiconductor memory device and operation method thereof Sep 5, 2012 Issued
Array ( [id] => 8565152 [patent_doc_number] => 20120327723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/600271 [patent_app_country] => US [patent_app_date] => 2012-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11276 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13600271 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/600271
Semiconductor device Aug 30, 2012 Issued
Array ( [id] => 10151633 [patent_doc_number] => 09183929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Systems, methods and devices for programming a multilevel resistive memory cell' [patent_app_type] => utility [patent_app_number] => 13/597639 [patent_app_country] => US [patent_app_date] => 2012-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5851 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13597639 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/597639
Systems, methods and devices for programming a multilevel resistive memory cell Aug 28, 2012 Issued
Array ( [id] => 9678642 [patent_doc_number] => 08817562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Devices and methods for controlling memory cell pre-charge operations' [patent_app_type] => utility [patent_app_number] => 13/563224 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3803 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13563224 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/563224
Devices and methods for controlling memory cell pre-charge operations Jul 30, 2012 Issued
Array ( [id] => 9442525 [patent_doc_number] => 08711648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Voltage generating system and memory device using the same' [patent_app_type] => utility [patent_app_number] => 13/563312 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4151 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13563312 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/563312
Voltage generating system and memory device using the same Jul 30, 2012 Issued
Array ( [id] => 8949081 [patent_doc_number] => 20130194861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'SINGLE-ENDED SRAM WITH CROSS-POINT DATA-AWARE WRITE OPERATION' [patent_app_type] => utility [patent_app_number] => 13/562330 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4231 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13562330 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/562330
Single-ended SRAM with cross-point data-aware write operation Jul 30, 2012 Issued
Array ( [id] => 9415227 [patent_doc_number] => 08699273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Bitline voltage regulation in non-volatile memory' [patent_app_type] => utility [patent_app_number] => 13/563206 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 13069 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13563206 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/563206
Bitline voltage regulation in non-volatile memory Jul 30, 2012 Issued
Array ( [id] => 8882600 [patent_doc_number] => 20130155784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/563014 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13563014 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/563014
Semiconductor memory apparatus Jul 30, 2012 Issued
Array ( [id] => 9292935 [patent_doc_number] => 20140036569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'RESISTIVE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/563290 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3737 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13563290 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/563290
Resistive memory device Jul 30, 2012 Issued
Array ( [id] => 9650427 [patent_doc_number] => 08804452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Data interleaving module' [patent_app_type] => utility [patent_app_number] => 13/562536 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7372 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13562536 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/562536
Data interleaving module Jul 30, 2012 Issued
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