Christy L. Novacek

Array ( [id] => 8550659 [patent_doc_number] => 08325547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-04 [patent_title] => 'Test apparatus and repair analysis method' [patent_app_type] => utility [patent_app_number] => 13/298207 [patent_app_country] => US [patent_app_date] => 2011-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8128 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13298207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8949101 [patent_doc_number] => 20130194881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'AREA-EFFICIENT MULTI-MODAL SIGNALING INTERFACE' [patent_app_type] => utility [patent_app_number] => 13/878419 [patent_app_country] => US [patent_app_date] => 2011-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5498 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13878419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9228547 [patent_doc_number] => 08634221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-21 [patent_title] => 'Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposer and that utilizes a SerDes interface to interface a memory controller with an integrated circuit, and a method' [patent_app_type] => utility [patent_app_number] => 13/286338 [patent_app_country] => US [patent_app_date] => 2011-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3763 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13286338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10833080 [patent_doc_number] => 08861259 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Resistance change memory cell circuits and methods' [patent_app_type] => utility [patent_app_number] => 13/882130 [patent_app_country] => US [patent_app_date] => 2011-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13882130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8922436 [patent_doc_number] => 08488379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => '5T high density nvDRAM cell' [patent_app_type] => utility [patent_app_number] => 13/270995 [patent_app_country] => US [patent_app_date] => 2011-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13270995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8396336 [patent_doc_number] => RE043665 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2012-09-18 [patent_title] => 'Reading non-volatile multilevel memory cells' [patent_app_type] => reissue [patent_app_number] => 13/268049 [patent_app_country] => US [patent_app_date] => 2011-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 12528 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13268049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8949106 [patent_doc_number] => 20130194886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'PHYSICAL UNCLONABLE FUNCTION WITH IMPROVED START-UP BEHAVIOR' [patent_app_type] => utility [patent_app_number] => 13/877656 [patent_app_country] => US [patent_app_date] => 2011-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 16512 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13877656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9764100 [patent_doc_number] => 08848436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Electric element' [patent_app_type] => utility [patent_app_number] => 13/877546 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 63 [patent_figures_cnt] => 116 [patent_no_of_words] => 26262 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13877546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8387491 [patent_doc_number] => 08264893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/238114 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 11379 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13238114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7708827 [patent_doc_number] => 20120002458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'RESISTANCE CHANGE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/231687 [patent_app_country] => US [patent_app_date] => 2011-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 23501 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13231687 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8573216 [patent_doc_number] => 08339869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Semiconductor device and data processor' [patent_app_type] => utility [patent_app_number] => 13/220747 [patent_app_country] => US [patent_app_date] => 2011-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7820 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13220747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8761770 [patent_doc_number] => 08422300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Non-volatile memory apparatus and methods' [patent_app_type] => utility [patent_app_number] => 13/219473 [patent_app_country] => US [patent_app_date] => 2011-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4662 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13219473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9292951 [patent_doc_number] => 20140036585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'NONVOLATILE MEMORY DEVICE USING A THRESHOLD VOLTAGE SWITCHING MATERIAL AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 13/876136 [patent_app_country] => US [patent_app_date] => 2011-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3130 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13876136 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9693605 [patent_doc_number] => 08824222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-02 [patent_title] => 'Fast-wake memory' [patent_app_type] => utility [patent_app_number] => 13/702112 [patent_app_country] => US [patent_app_date] => 2011-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 34069 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13702112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8636226 [patent_doc_number] => 20130028029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'METHOD OF CONTROLLING OPERATIONS OF A DELAY LOCKED LOOP OF A DYNAMIC RANDOM ACCESS MEMORY' [patent_app_type] => utility [patent_app_number] => 13/192468 [patent_app_country] => US [patent_app_date] => 2011-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4240 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13192468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9168185 [patent_doc_number] => 08593869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Apparatuses and methods including memory array and data line architecture' [patent_app_type] => utility [patent_app_number] => 13/192248 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 17517 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13192248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9256043 [patent_doc_number] => 08619471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'Apparatuses and methods including memory array data line selection' [patent_app_type] => utility [patent_app_number] => 13/192280 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 18140 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13192280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8636214 [patent_doc_number] => 20130028017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'DETERMINING AND TRANSFERRING DATA FROM A MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 13/191836 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6499 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13191836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8944961 [patent_doc_number] => 08498144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-30 [patent_title] => 'Semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 13/191678 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4368 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13191678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8798285 [patent_doc_number] => 08437164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-07 [patent_title] => 'Stacked memory device for a configurable bandwidth memory interface' [patent_app_type] => utility [patent_app_number] => 13/191624 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4743 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13191624 [rel_patent_id] =>[rel_patent_doc_number] =>)