Search

Christy L. Novacek

Examiner (ID: 17383)

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
465
Issued Applications
357
Pending Applications
12
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8631359 [patent_doc_number] => 08363443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross-point arrays' [patent_app_type] => utility [patent_app_number] => 12/931422 [patent_app_country] => US [patent_app_date] => 2011-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 10865 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12931422 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/931422
Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross-point arrays Jan 30, 2011 Issued
Array ( [id] => 8459433 [patent_doc_number] => 08295109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Replacing defective columns of memory cells in response to external addresses' [patent_app_type] => utility [patent_app_number] => 13/017168 [patent_app_country] => US [patent_app_date] => 2011-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13017168 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/017168
Replacing defective columns of memory cells in response to external addresses Jan 30, 2011 Issued
Array ( [id] => 8654272 [patent_doc_number] => 08374028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-12 [patent_title] => 'Sense operation in a memory device' [patent_app_type] => utility [patent_app_number] => 13/009540 [patent_app_country] => US [patent_app_date] => 2011-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3627 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13009540 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/009540
Sense operation in a memory device Jan 18, 2011 Issued
Array ( [id] => 8726911 [patent_doc_number] => 08406045 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-26 [patent_title] => 'Three terminal magnetic element' [patent_app_type] => utility [patent_app_number] => 13/009818 [patent_app_country] => US [patent_app_date] => 2011-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4881 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13009818 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/009818
Three terminal magnetic element Jan 18, 2011 Issued
Array ( [id] => 8622361 [patent_doc_number] => 08355277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-15 [patent_title] => 'Biasing circuit and technique for SRAM data retention' [patent_app_type] => utility [patent_app_number] => 13/008992 [patent_app_country] => US [patent_app_date] => 2011-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13008992 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/008992
Biasing circuit and technique for SRAM data retention Jan 18, 2011 Issued
Array ( [id] => 5957723 [patent_doc_number] => 20110182110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/009034 [patent_app_country] => US [patent_app_date] => 2011-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14934 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20110182110.pdf [firstpage_image] =>[orig_patent_app_number] => 13009034 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/009034
Semiconductor memory device and driving method thereof Jan 18, 2011 Issued
Array ( [id] => 8579285 [patent_doc_number] => 08345504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Data-aware dynamic supply random access memory' [patent_app_type] => utility [patent_app_number] => 13/009240 [patent_app_country] => US [patent_app_date] => 2011-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11542 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13009240 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/009240
Data-aware dynamic supply random access memory Jan 18, 2011 Issued
Array ( [id] => 8300259 [patent_doc_number] => 20120182808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'Memory Device, Manufacturing Method and Operating Method of the Same' [patent_app_type] => utility [patent_app_number] => 13/009464 [patent_app_country] => US [patent_app_date] => 2011-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4584 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13009464 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/009464
Memory device, manufacturing method and operating method of the same Jan 18, 2011 Issued
Array ( [id] => 8593381 [patent_doc_number] => 08351258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-08 [patent_title] => 'Adapting read reference voltage in flash memory device' [patent_app_type] => utility [patent_app_number] => 13/008958 [patent_app_country] => US [patent_app_date] => 2011-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5808 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13008958 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/008958
Adapting read reference voltage in flash memory device Jan 18, 2011 Issued
Array ( [id] => 6172832 [patent_doc_number] => 20110176379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY OF OPEN BIT LINE TYPE AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/008408 [patent_app_country] => US [patent_app_date] => 2011-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8143 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20110176379.pdf [firstpage_image] =>[orig_patent_app_number] => 13008408 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/008408
SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY OF OPEN BIT LINE TYPE AND CONTROL METHOD THEREOF Jan 17, 2011 Abandoned
Array ( [id] => 6053795 [patent_doc_number] => 20110110155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE' [patent_app_type] => utility [patent_app_number] => 13/005774 [patent_app_country] => US [patent_app_date] => 2011-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20110110155.pdf [firstpage_image] =>[orig_patent_app_number] => 13005774 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/005774
Stacked semiconductor devices including a master device Jan 12, 2011 Issued
Array ( [id] => 5966857 [patent_doc_number] => 20110149644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'VOLTAGE CONTROL CIRCUIT FOR PHASE CHANGE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/971578 [patent_app_country] => US [patent_app_date] => 2010-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3468 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20110149644.pdf [firstpage_image] =>[orig_patent_app_number] => 12971578 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/971578
Voltage control circuit for phase change memory Dec 16, 2010 Issued
Array ( [id] => 5966873 [patent_doc_number] => 20110149652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/971208 [patent_app_country] => US [patent_app_date] => 2010-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12519 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20110149652.pdf [firstpage_image] =>[orig_patent_app_number] => 12971208 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/971208
Semiconductor memory device and method of operating the same Dec 16, 2010 Issued
Array ( [id] => 8573190 [patent_doc_number] => 08339843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Generating a temperature-compensated write current for a magnetic memory cell' [patent_app_type] => utility [patent_app_number] => 12/971244 [patent_app_country] => US [patent_app_date] => 2010-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 13982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12971244 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/971244
Generating a temperature-compensated write current for a magnetic memory cell Dec 16, 2010 Issued
Array ( [id] => 8068185 [patent_doc_number] => 20110242928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'ADDRESS DELAY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/970792 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4019 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20110242928.pdf [firstpage_image] =>[orig_patent_app_number] => 12970792 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970792
Address delay circuit of semiconductor memory apparatus Dec 15, 2010 Issued
Array ( [id] => 8556664 [patent_doc_number] => 08331142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Memory' [patent_app_type] => utility [patent_app_number] => 12/970744 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4631 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12970744 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970744
Memory Dec 15, 2010 Issued
Array ( [id] => 8644165 [patent_doc_number] => 08369159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Input/output circuit and method of semiconductor apparatus and system with the same' [patent_app_type] => utility [patent_app_number] => 12/970934 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 15365 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12970934 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970934
Input/output circuit and method of semiconductor apparatus and system with the same Dec 15, 2010 Issued
Array ( [id] => 8534735 [patent_doc_number] => 08310894 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-11-13 [patent_title] => 'Write-assist and power-down circuit for low power SRAM applications' [patent_app_type] => utility [patent_app_number] => 12/946534 [patent_app_country] => US [patent_app_date] => 2010-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4012 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12946534 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/946534
Write-assist and power-down circuit for low power SRAM applications Nov 14, 2010 Issued
Array ( [id] => 8750781 [patent_doc_number] => 08416620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Magnetic stack having assist layer' [patent_app_type] => utility [patent_app_number] => 12/943976 [patent_app_country] => US [patent_app_date] => 2010-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 5253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12943976 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/943976
Magnetic stack having assist layer Nov 10, 2010 Issued
Array ( [id] => 8631358 [patent_doc_number] => 08363442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'NAND based resistive sense memory cell architecture' [patent_app_type] => utility [patent_app_number] => 12/903716 [patent_app_country] => US [patent_app_date] => 2010-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4419 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12903716 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/903716
NAND based resistive sense memory cell architecture Oct 12, 2010 Issued
Menu