Christy L. Novacek

Array ( [id] => 8125301 [patent_doc_number] => 20120087199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'WAKE-UP CONTROL CIRCUIT FOR POWER-GATED IC' [patent_app_type] => utility [patent_app_number] => 12/900840 [patent_app_country] => US [patent_app_date] => 2010-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3358 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20120087199.pdf [firstpage_image] =>[orig_patent_app_number] => 12900840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8539398 [patent_doc_number] => 08315121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Internal power generating apparatus, multichannel memory including the same, and processing system employing the multichannel memory' [patent_app_type] => utility [patent_app_number] => 12/900624 [patent_app_country] => US [patent_app_date] => 2010-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4799 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12900624 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8125281 [patent_doc_number] => 20120087188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'STRUCTURE AND INHIBITED OPERATION OF FLASH MEMORY WITH SPLIT GATE' [patent_app_type] => utility [patent_app_number] => 12/900608 [patent_app_country] => US [patent_app_date] => 2010-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7186 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20120087188.pdf [firstpage_image] =>[orig_patent_app_number] => 12900608 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8539356 [patent_doc_number] => 08315079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Circuit for concurrent read operation and method therefor' [patent_app_type] => utility [patent_app_number] => 12/900232 [patent_app_country] => US [patent_app_date] => 2010-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12900232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8245943 [patent_doc_number] => 08203874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-19 [patent_title] => 'Staggered magnetic tunnel junction' [patent_app_type] => utility [patent_app_number] => 12/898831 [patent_app_country] => US [patent_app_date] => 2010-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5450 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/203/08203874.pdf [firstpage_image] =>[orig_patent_app_number] => 12898831 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8258823 [patent_doc_number] => 08208332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Temperature compensation circuit and method for sensing memory' [patent_app_type] => utility [patent_app_number] => 12/870313 [patent_app_country] => US [patent_app_date] => 2010-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2213 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12870313 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8258794 [patent_doc_number] => 08208299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Integrated circuit embedded with non-volatile programmable memory having variable coupling and separate read/write paths' [patent_app_type] => utility [patent_app_number] => 12/869378 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6291 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12869378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6385025 [patent_doc_number] => 20100302857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'METHOD OF PROGRAMMING AN ARRAY OF NMOS EEPROM CELLS THAT MINIMIZES BIT DISTURBANCES AND VOLTAGE WITHSTAND REQUIREMENTS FOR THE MEMORY ARRAY AND SUPPORTING CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/854504 [patent_app_country] => US [patent_app_date] => 2010-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5296 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20100302857.pdf [firstpage_image] =>[orig_patent_app_number] => 12854504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9052994 [patent_doc_number] => 20130250708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'MEMORY ELEMENT AND METHOD FOR DETERMINING THE DATA STATE OF A MEMORY ELEMENT' [patent_app_type] => utility [patent_app_number] => 13/383602 [patent_app_country] => US [patent_app_date] => 2010-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4859 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13383602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4598571 [patent_doc_number] => 07983070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'DRAM tunneling access transistor' [patent_app_type] => utility [patent_app_number] => 12/843392 [patent_app_country] => US [patent_app_date] => 2010-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4057 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/983/07983070.pdf [firstpage_image] =>[orig_patent_app_number] => 12843392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8195330 [patent_doc_number] => 20120120717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'SRAM CELL' [patent_app_type] => utility [patent_app_number] => 13/384648 [patent_app_country] => US [patent_app_date] => 2010-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20120120717.pdf [firstpage_image] =>[orig_patent_app_number] => 13384648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8204568 [patent_doc_number] => 08189374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Memory device including an electrode having an outer portion with greater resistivity' [patent_app_type] => utility [patent_app_number] => 12/826201 [patent_app_country] => US [patent_app_date] => 2010-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/189/08189374.pdf [firstpage_image] =>[orig_patent_app_number] => 12826201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8216673 [patent_doc_number] => 08194450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Methods and control circuitry for programming memory cells' [patent_app_type] => utility [patent_app_number] => 12/815979 [patent_app_country] => US [patent_app_date] => 2010-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5646 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/194/08194450.pdf [firstpage_image] =>[orig_patent_app_number] => 12815979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6571052 [patent_doc_number] => 20100290262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-18 [patent_title] => 'Three dimensional hexagonal matrix memory array' [patent_app_type] => utility [patent_app_number] => 12/801504 [patent_app_country] => US [patent_app_date] => 2010-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9894 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20100290262.pdf [firstpage_image] =>[orig_patent_app_number] => 12801504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8820008 [patent_doc_number] => 20130121054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'THREE-DIMENSIONAL INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/700224 [patent_app_country] => US [patent_app_date] => 2010-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3471 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13700224 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6037695 [patent_doc_number] => 20110090744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'CHANNEL PRECHARGE AND PROGRAM METHODS OF A NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/795196 [patent_app_country] => US [patent_app_date] => 2010-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7926 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20110090744.pdf [firstpage_image] =>[orig_patent_app_number] => 12795196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8714683 [patent_doc_number] => 08400827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Non-volatile memory programming' [patent_app_type] => utility [patent_app_number] => 12/795202 [patent_app_country] => US [patent_app_date] => 2010-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6285 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12795202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6023196 [patent_doc_number] => 20110051522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'METHOD OF PROGRAMMING FLASH MEMORY OF THE DIFFERENTIAL CELL STRUCTURES FOR BETTER ENDURANCE' [patent_app_type] => utility [patent_app_number] => 12/794698 [patent_app_country] => US [patent_app_date] => 2010-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20110051522.pdf [firstpage_image] =>[orig_patent_app_number] => 12794698 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8307204 [patent_doc_number] => 08228749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-24 [patent_title] => 'Margin testing of static random access memory cells' [patent_app_type] => utility [patent_app_number] => 12/794139 [patent_app_country] => US [patent_app_date] => 2010-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 17838 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12794139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8798326 [patent_doc_number] => 08437204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-07 [patent_title] => 'Memory array with corresponding row and column control signals' [patent_app_type] => utility [patent_app_number] => 12/792944 [patent_app_country] => US [patent_app_date] => 2010-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12792944 [rel_patent_id] =>[rel_patent_doc_number] =>)