Christy L. Novacek

Array ( [id] => 4544368 [patent_doc_number] => 07889550 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-15 [patent_title] => 'Control driver for memory and related method' [patent_app_type] => utility [patent_app_number] => 12/541976 [patent_app_country] => US [patent_app_date] => 2009-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3566 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/889/07889550.pdf [firstpage_image] =>[orig_patent_app_number] => 12541976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4598606 [patent_doc_number] => 07983094 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-19 [patent_title] => 'PVT compensated auto-calibration scheme for DDR3' [patent_app_type] => utility [patent_app_number] => 12/539594 [patent_app_country] => US [patent_app_date] => 2009-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 10140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/983/07983094.pdf [firstpage_image] =>[orig_patent_app_number] => 12539594 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4615339 [patent_doc_number] => 07990786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Read-leveling implementations for DDR3 applications on an FPGA' [patent_app_type] => utility [patent_app_number] => 12/539582 [patent_app_country] => US [patent_app_date] => 2009-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 8742 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/990/07990786.pdf [firstpage_image] =>[orig_patent_app_number] => 12539582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4582594 [patent_doc_number] => 07830733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Devices, systems, and methods for independent output drive strengths' [patent_app_type] => utility [patent_app_number] => 12/538559 [patent_app_country] => US [patent_app_date] => 2009-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/830/07830733.pdf [firstpage_image] =>[orig_patent_app_number] => 12538559 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5366215 [patent_doc_number] => 20090303774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'METHODS OF OPERATING A BISTABLE RESISTANCE RANDOM ACCESS MEMORY WITH MULTIPLE MEMORY LAYERS AND MULTILEVEL MEMORY STATES' [patent_app_type] => utility [patent_app_number] => 12/511846 [patent_app_country] => US [patent_app_date] => 2009-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15215 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20090303774.pdf [firstpage_image] =>[orig_patent_app_number] => 12511846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4452863 [patent_doc_number] => 07965550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Multi-level cell access buffer with dual function' [patent_app_type] => utility [patent_app_number] => 12/499577 [patent_app_country] => US [patent_app_date] => 2009-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6064 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/965/07965550.pdf [firstpage_image] =>[orig_patent_app_number] => 12499577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6571260 [patent_doc_number] => 20100290280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-18 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/494344 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4586 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20100290280.pdf [firstpage_image] =>[orig_patent_app_number] => 12494344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6337832 [patent_doc_number] => 20100329063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'DYNAMICALLY CONTROLLED VOLTAGE REGULATOR FOR A MEMORY' [patent_app_type] => utility [patent_app_number] => 12/494700 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0329/20100329063.pdf [firstpage_image] =>[orig_patent_app_number] => 12494700 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6571477 [patent_doc_number] => 20100290302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-18 [patent_title] => 'FUSE CIRCUIT AND DRIVING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/494616 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20100290302.pdf [firstpage_image] =>[orig_patent_app_number] => 12494616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6233426 [patent_doc_number] => 20100265761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY CIRCUIT FOR GENERATING WRITE VOLTAGE' [patent_app_type] => utility [patent_app_number] => 12/494362 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5901 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20100265761.pdf [firstpage_image] =>[orig_patent_app_number] => 12494362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4507040 [patent_doc_number] => 07920437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-05 [patent_title] => 'Address control circuit of semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 12/494474 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3334 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/920/07920437.pdf [firstpage_image] =>[orig_patent_app_number] => 12494474 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5494553 [patent_doc_number] => 20090262581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'NON VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/493143 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13376 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20090262581.pdf [firstpage_image] =>[orig_patent_app_number] => 12493143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4491704 [patent_doc_number] => 07903449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/485568 [patent_app_country] => US [patent_app_date] => 2009-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4684 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/903/07903449.pdf [firstpage_image] =>[orig_patent_app_number] => 12485568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5372866 [patent_doc_number] => 20090310426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/485566 [patent_app_country] => US [patent_app_date] => 2009-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4293 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0310/20090310426.pdf [firstpage_image] =>[orig_patent_app_number] => 12485566 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6411970 [patent_doc_number] => 20100149880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'WINDOW ENLARGEMENT BY SELECTIVE ERASE OF NON-VOLATILE MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 12/485510 [patent_app_country] => US [patent_app_date] => 2009-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9051 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20100149880.pdf [firstpage_image] =>[orig_patent_app_number] => 12485510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6403572 [patent_doc_number] => 20100165720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'VERIFICATION CIRCUITS AND METHODS FOR PHASE CHANGE MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 12/485720 [patent_app_country] => US [patent_app_date] => 2009-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3355 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20100165720.pdf [firstpage_image] =>[orig_patent_app_number] => 12485720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6374795 [patent_doc_number] => 20100315874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'USE OF EMERGING NON-VOLATILE MEMORY ELEMENTS WITH FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 12/484418 [patent_app_country] => US [patent_app_date] => 2009-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3484 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20100315874.pdf [firstpage_image] =>[orig_patent_app_number] => 12484418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6374676 [patent_doc_number] => 20100315852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'MEMORY AND STORAGE DEVICE UTILIZING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/484088 [patent_app_country] => US [patent_app_date] => 2009-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2193 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20100315852.pdf [firstpage_image] =>[orig_patent_app_number] => 12484088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4458938 [patent_doc_number] => 07894231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Memory module and data input/output system' [patent_app_type] => utility [patent_app_number] => 12/483328 [patent_app_country] => US [patent_app_date] => 2009-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4973 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/894/07894231.pdf [firstpage_image] =>[orig_patent_app_number] => 12483328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6403923 [patent_doc_number] => 20100165774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'SMALL-SIZED FUSE BOX AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/483440 [patent_app_country] => US [patent_app_date] => 2009-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3304 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20100165774.pdf [firstpage_image] =>[orig_patent_app_number] => 12483440 [rel_patent_id] =>[rel_patent_doc_number] =>)