Search

Christy L. Novacek

Examiner (ID: 13644)

Most Active Art Unit
2822
Art Unit(s)
2822
Total Applications
465
Issued Applications
357
Pending Applications
12
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5916621 [patent_doc_number] => 20060237816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Semiconductor device and manufacturing method for the same' [patent_app_type] => utility [patent_app_number] => 11/395278 [patent_app_country] => US [patent_app_date] => 2006-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20060237816.pdf [firstpage_image] =>[orig_patent_app_number] => 11395278 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/395278
Semiconductor device and manufacturing method for the same Apr 2, 2006 Issued
Array ( [id] => 4492645 [patent_doc_number] => 07955900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Coated thermal interface in integrated circuit die' [patent_app_type] => utility [patent_app_number] => 11/278337 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4265 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/955/07955900.pdf [firstpage_image] =>[orig_patent_app_number] => 11278337 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/278337
Coated thermal interface in integrated circuit die Mar 30, 2006 Issued
Array ( [id] => 369781 [patent_doc_number] => 07476554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-13 [patent_title] => 'Substrate processing method' [patent_app_type] => utility [patent_app_number] => 11/389117 [patent_app_country] => US [patent_app_date] => 2006-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5834 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/476/07476554.pdf [firstpage_image] =>[orig_patent_app_number] => 11389117 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/389117
Substrate processing method Mar 26, 2006 Issued
Array ( [id] => 810540 [patent_doc_number] => 07417297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-26 [patent_title] => 'Film or layer of semiconducting material, and process for producing the film or layer' [patent_app_type] => utility [patent_app_number] => 11/384887 [patent_app_country] => US [patent_app_date] => 2006-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5486 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/417/07417297.pdf [firstpage_image] =>[orig_patent_app_number] => 11384887 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/384887
Film or layer of semiconducting material, and process for producing the film or layer Mar 19, 2006 Issued
Array ( [id] => 288963 [patent_doc_number] => 07547576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-16 [patent_title] => 'Solder wall structure in flip-chip technologies' [patent_app_type] => utility [patent_app_number] => 11/275867 [patent_app_country] => US [patent_app_date] => 2006-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2233 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/547/07547576.pdf [firstpage_image] =>[orig_patent_app_number] => 11275867 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/275867
Solder wall structure in flip-chip technologies Jan 31, 2006 Issued
Array ( [id] => 274223 [patent_doc_number] => 07560387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-14 [patent_title] => 'Opening hard mask and SOI substrate in single process chamber' [patent_app_type] => utility [patent_app_number] => 11/275707 [patent_app_country] => US [patent_app_date] => 2006-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1833 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/560/07560387.pdf [firstpage_image] =>[orig_patent_app_number] => 11275707 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/275707
Opening hard mask and SOI substrate in single process chamber Jan 24, 2006 Issued
Array ( [id] => 573883 [patent_doc_number] => 07459394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Methods of manufacturing semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/324760 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 587 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/459/07459394.pdf [firstpage_image] =>[orig_patent_app_number] => 11324760 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/324760
Methods of manufacturing semiconductor devices Jan 2, 2006 Issued
Array ( [id] => 334210 [patent_doc_number] => 07507621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/322287 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 10165 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/507/07507621.pdf [firstpage_image] =>[orig_patent_app_number] => 11322287 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/322287
Method of manufacturing semiconductor device Jan 2, 2006 Issued
Array ( [id] => 555801 [patent_doc_number] => 07468325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-23 [patent_title] => 'Method of cleaning silicon nitride layer' [patent_app_type] => utility [patent_app_number] => 11/319617 [patent_app_country] => US [patent_app_date] => 2005-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1629 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/468/07468325.pdf [firstpage_image] =>[orig_patent_app_number] => 11319617 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/319617
Method of cleaning silicon nitride layer Dec 28, 2005 Issued
Array ( [id] => 204583 [patent_doc_number] => 07629252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-08 [patent_title] => 'Conformal electroless deposition of barrier layer materials' [patent_app_type] => utility [patent_app_number] => 11/318137 [patent_app_country] => US [patent_app_date] => 2005-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3180 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/629/07629252.pdf [firstpage_image] =>[orig_patent_app_number] => 11318137 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/318137
Conformal electroless deposition of barrier layer materials Dec 22, 2005 Issued
Array ( [id] => 5596408 [patent_doc_number] => 20060160325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/312387 [patent_app_country] => US [patent_app_date] => 2005-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1273 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20060160325.pdf [firstpage_image] =>[orig_patent_app_number] => 11312387 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/312387
Method of manufacturing semiconductor device Dec 20, 2005 Abandoned
Array ( [id] => 5171949 [patent_doc_number] => 20070072382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/302197 [patent_app_country] => US [patent_app_date] => 2005-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072382.pdf [firstpage_image] =>[orig_patent_app_number] => 11302197 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/302197
Method of manufacturing semiconductor device Dec 13, 2005 Abandoned
Array ( [id] => 5253461 [patent_doc_number] => 20070134917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Partial-via-first dual-damascene process with tri-layer resist approach' [patent_app_type] => utility [patent_app_number] => 11/301917 [patent_app_country] => US [patent_app_date] => 2005-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20070134917.pdf [firstpage_image] =>[orig_patent_app_number] => 11301917 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/301917
Partial-via-first dual-damascene process with tri-layer resist approach Dec 12, 2005 Abandoned
Array ( [id] => 1076925 [patent_doc_number] => 07615438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-10 [patent_title] => 'Lanthanide yttrium aluminum oxide dielectric films' [patent_app_type] => utility [patent_app_number] => 11/297567 [patent_app_country] => US [patent_app_date] => 2005-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 10030 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/615/07615438.pdf [firstpage_image] =>[orig_patent_app_number] => 11297567 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/297567
Lanthanide yttrium aluminum oxide dielectric films Dec 7, 2005 Issued
Array ( [id] => 5712677 [patent_doc_number] => 20060076040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'Semiconductive substrate cleaning systems' [patent_app_type] => utility [patent_app_number] => 11/290339 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5609 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20060076040.pdf [firstpage_image] =>[orig_patent_app_number] => 11290339 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/290339
Semiconductive substrate cleaning systems Nov 29, 2005 Abandoned
Array ( [id] => 578800 [patent_doc_number] => 07452751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/281727 [patent_app_country] => US [patent_app_date] => 2005-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 94 [patent_no_of_words] => 16565 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 417 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/452/07452751.pdf [firstpage_image] =>[orig_patent_app_number] => 11281727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/281727
Semiconductor device and method of manufacturing the same Nov 17, 2005 Issued
Array ( [id] => 267057 [patent_doc_number] => 07566582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-28 [patent_title] => 'Systems, methods and devices relating to actuatably moveable machines' [patent_app_type] => utility [patent_app_number] => 11/258688 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 61 [patent_no_of_words] => 18986 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/566/07566582.pdf [firstpage_image] =>[orig_patent_app_number] => 11258688 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258688
Systems, methods and devices relating to actuatably moveable machines Oct 24, 2005 Issued
Array ( [id] => 5193995 [patent_doc_number] => 20070082479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Chemical mechanical polishing techniques for integrated circuit fabrication' [patent_app_type] => utility [patent_app_number] => 11/245677 [patent_app_country] => US [patent_app_date] => 2005-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20070082479.pdf [firstpage_image] =>[orig_patent_app_number] => 11245677 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/245677
Chemical mechanical polishing techniques for integrated circuit fabrication Oct 5, 2005 Abandoned
Array ( [id] => 5168128 [patent_doc_number] => 20070068559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method and apparatus for electronic device manufacture using shadow masks' [patent_app_type] => utility [patent_app_number] => 11/236937 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6942 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20070068559.pdf [firstpage_image] =>[orig_patent_app_number] => 11236937 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/236937
Method and apparatus for electronic device manufacture using shadow masks Sep 26, 2005 Issued
Array ( [id] => 5694291 [patent_doc_number] => 20060154438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Method for manufacturing semiconductor device with trenches in substrate surface' [patent_app_type] => utility [patent_app_number] => 11/233377 [patent_app_country] => US [patent_app_date] => 2005-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6135 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20060154438.pdf [firstpage_image] =>[orig_patent_app_number] => 11233377 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/233377
Method for manufacturing a semiconductor device having trenches defined in the substrate surface Sep 22, 2005 Issued
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