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Chuck Y Mah

Examiner (ID: 12458, Phone: (571)272-7059 , Office: P/3677 )

Most Active Art Unit
3677
Art Unit(s)
3626, 3209, 3676, 3677, 3205
Total Applications
3834
Issued Applications
3134
Pending Applications
144
Abandoned Applications
549

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17589622 [patent_doc_number] => 11327895 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-10 [patent_title] => Protocol for processing requests that assigns each request received by a node a sequence identifier, stores data written by the request in a cache page block, stores a descriptor for the request in a cache page descriptor, and returns a completion acknowledgement of the request [patent_app_type] => utility [patent_app_number] => 17/191755 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 17033 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17191755 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/191755
Protocol for processing requests that assigns each request received by a node a sequence identifier, stores data written by the request in a cache page block, stores a descriptor for the request in a cache page descriptor, and returns a completion acknowledgement of the request Mar 3, 2021 Issued
Array ( [id] => 16423679 [patent_doc_number] => 20200348877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => SERVER AND ASSOCIATED COMPUTER PROGRAM PRODUCT [patent_app_type] => utility [patent_app_number] => 16/935130 [patent_app_country] => US [patent_app_date] => 2020-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16935130 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/935130
Server and associated computer program product using different transmission speed for different portions of cold data Jul 20, 2020 Issued
Array ( [id] => 17364861 [patent_doc_number] => 11231882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Data storage device with improved read performance and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/909523 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8064 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909523 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/909523
Data storage device with improved read performance and operating method thereof Jun 22, 2020 Issued
Array ( [id] => 17437596 [patent_doc_number] => 11262928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Storage system and method for enabling partial defragmentation prior to reading in burst mode [patent_app_type] => utility [patent_app_number] => 16/899992 [patent_app_country] => US [patent_app_date] => 2020-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899992 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/899992
Storage system and method for enabling partial defragmentation prior to reading in burst mode Jun 11, 2020 Issued
Array ( [id] => 16423643 [patent_doc_number] => 20200348841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => DATA BLOCK MATRIX [patent_app_type] => utility [patent_app_number] => 16/861309 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11485 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 703 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861309 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/861309
Diagonal node data block matrix for adding hash-linked records and deleting arbitrary records while preserving hash-based integrity assurance Apr 28, 2020 Issued
Array ( [id] => 17621757 [patent_doc_number] => 11340811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Determining reclaim information for a storage block based on data length and matching write and delete parameters [patent_app_type] => utility [patent_app_number] => 16/829910 [patent_app_country] => US [patent_app_date] => 2020-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5727 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16829910 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/829910
Determining reclaim information for a storage block based on data length and matching write and delete parameters Mar 24, 2020 Issued
Array ( [id] => 17164941 [patent_doc_number] => 11151039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Apparatus and method for maintaining cache coherence data for memory blocks of different size granularities using a snoop filter storage comprising an n-way set associative storage structure [patent_app_type] => utility [patent_app_number] => 16/821271 [patent_app_country] => US [patent_app_date] => 2020-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9596 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16821271 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/821271
Apparatus and method for maintaining cache coherence data for memory blocks of different size granularities using a snoop filter storage comprising an n-way set associative storage structure Mar 16, 2020 Issued
Array ( [id] => 16600036 [patent_doc_number] => 20210026567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => STORAGE SYSTEM INCLUDING NONVOLATILE MEMORY MODULE AND OPERATING METHOD OF THE NONVOLATILE MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 16/814281 [patent_app_country] => US [patent_app_date] => 2020-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16814281 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/814281
Storage system including nonvolatile memory module for converting random logical addresses to sequential logical addresses and operating method of the nonvolatile memory module Mar 9, 2020 Issued
Array ( [id] => 17469220 [patent_doc_number] => 11275697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Translation lookaside buffer invalidation for merged invalidation requests across power boundaries [patent_app_type] => utility [patent_app_number] => 16/786231 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786231 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/786231
Translation lookaside buffer invalidation for merged invalidation requests across power boundaries Feb 9, 2020 Issued
Array ( [id] => 17136389 [patent_doc_number] => 11137942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => Memory system, memory controller, and method of operating a memory system for determining a number of hit and miss requests about map segments in a map cache and determining whether or not to perform data read operation in parallel [patent_app_type] => utility [patent_app_number] => 16/749530 [patent_app_country] => US [patent_app_date] => 2020-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16749530 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/749530
Memory system, memory controller, and method of operating a memory system for determining a number of hit and miss requests about map segments in a map cache and determining whether or not to perform data read operation in parallel Jan 21, 2020 Issued
Array ( [id] => 16964958 [patent_doc_number] => 20210216457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => EARLY COMMITMENT OF A STORE-CONDITIONAL REQUEST [patent_app_type] => utility [patent_app_number] => 16/742380 [patent_app_country] => US [patent_app_date] => 2020-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16742380 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/742380
Completion logic performing early commitment of a store-conditional access based on a flag Jan 13, 2020 Issued
Array ( [id] => 16675474 [patent_doc_number] => 20210064240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => DATA STORAGE SYSTEM HAVING DUAL CHANNELS [patent_app_type] => utility [patent_app_number] => 16/682352 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682352 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682352
Data storage system capable of using high speed channel to access data, and using low speed channel to manage data exchanging, copying, and moving Nov 12, 2019 Issued
Array ( [id] => 17076802 [patent_doc_number] => 11113202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Operating method forcing the second operation to fail using a scatter-gather buffer and memory system thereof [patent_app_type] => utility [patent_app_number] => 16/682648 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 13451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682648 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682648
Operating method forcing the second operation to fail using a scatter-gather buffer and memory system thereof Nov 12, 2019 Issued
Array ( [id] => 17151169 [patent_doc_number] => 11144246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Memory system using available bad block based on data storage reliability and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/670562 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5177 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670562 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670562
Memory system using available bad block based on data storage reliability and operating method thereof Oct 30, 2019 Issued
Array ( [id] => 17283142 [patent_doc_number] => 11200171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Memory systems having a cache system and a host controller having a host queue [patent_app_type] => utility [patent_app_number] => 16/664095 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10876 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16664095 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/664095
Memory systems having a cache system and a host controller having a host queue Oct 24, 2019 Issued
Array ( [id] => 16910407 [patent_doc_number] => 11042447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Retention rule compliance of record deletion based on deletion log [patent_app_type] => utility [patent_app_number] => 16/586238 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586238 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586238
Retention rule compliance of record deletion based on deletion log Sep 26, 2019 Issued
Array ( [id] => 17031597 [patent_doc_number] => 11093409 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-17 [patent_title] => Using emulation of storage characteristics to perform an access request translated between different protocols [patent_app_type] => utility [patent_app_number] => 16/584864 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584864 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/584864
Using emulation of storage characteristics to perform an access request translated between different protocols Sep 25, 2019 Issued
Array ( [id] => 16192760 [patent_doc_number] => 20200233609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => METHOD AND APPARATUS FOR PERFORMING PIPELINE-BASED ACCESSING MANAGEMENT IN A STORAGE SERVER [patent_app_type] => utility [patent_app_number] => 16/581769 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16581769 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/581769
Method and apparatus for performing pipeline-based accessing management in a storage server with aid of caching metadata with cache module which is hardware pipeline module during processing object write command Sep 24, 2019 Issued
Array ( [id] => 16833838 [patent_doc_number] => 11010089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Approximating replication lag in cross-zone replicated block storage devices [patent_app_type] => utility [patent_app_number] => 16/579620 [patent_app_country] => US [patent_app_date] => 2019-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 30069 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16579620 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/579620
Approximating replication lag in cross-zone replicated block storage devices Sep 22, 2019 Issued
Array ( [id] => 16722325 [patent_doc_number] => 20210089472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => CONTROLLING CACHE ENTRY REPLACEMENT BASED ON USEFULNESS OF CACHE ENTRY [patent_app_type] => utility [patent_app_number] => 16/577271 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16577271 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/577271
Controlling cache entry replacement based on usefulness of cache entry Sep 19, 2019 Issued
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