Search

Chuck Y. Mah

Examiner (ID: 7555, Phone: (571)272-7059 , Office: P/3677 )

Most Active Art Unit
3677
Art Unit(s)
3209, 3626, 3205, 3676, 3677
Total Applications
3994
Issued Applications
3295
Pending Applications
173
Abandoned Applications
568

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5636141 [patent_doc_number] => 20060067114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Storage apparatus and semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 11/225593 [patent_app_country] => US [patent_app_date] => 2005-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6714 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20060067114.pdf [firstpage_image] =>[orig_patent_app_number] => 11225593 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/225593
Storage apparatus and semiconductor apparatus Sep 12, 2005 Issued
Array ( [id] => 531468 [patent_doc_number] => 07187580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Magnetic memory with structure providing reduced coercivity' [patent_app_type] => utility [patent_app_number] => 11/222623 [patent_app_country] => US [patent_app_date] => 2005-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4520 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187580.pdf [firstpage_image] =>[orig_patent_app_number] => 11222623 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/222623
Magnetic memory with structure providing reduced coercivity Sep 8, 2005 Issued
Array ( [id] => 5698776 [patent_doc_number] => 20060215460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'METHOD OF OPERATING P-CHANNEL MEMORY' [patent_app_type] => utility [patent_app_number] => 11/162365 [patent_app_country] => US [patent_app_date] => 2005-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20060215460.pdf [firstpage_image] =>[orig_patent_app_number] => 11162365 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/162365
Method of operating p-channel memory Sep 7, 2005 Issued
Array ( [id] => 459580 [patent_doc_number] => 07245517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Ferroelectric random access memory' [patent_app_type] => utility [patent_app_number] => 11/220853 [patent_app_country] => US [patent_app_date] => 2005-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 11449 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/245/07245517.pdf [firstpage_image] =>[orig_patent_app_number] => 11220853 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/220853
Ferroelectric random access memory Sep 7, 2005 Issued
Array ( [id] => 5709233 [patent_doc_number] => 20060050578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Decoder of semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/218717 [patent_app_country] => US [patent_app_date] => 2005-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7422 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20060050578.pdf [firstpage_image] =>[orig_patent_app_number] => 11218717 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/218717
Decoder of semiconductor memory device Sep 5, 2005 Issued
Array ( [id] => 5170298 [patent_doc_number] => 20070070729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'High access speed flash controller' [patent_app_type] => utility [patent_app_number] => 11/217503 [patent_app_country] => US [patent_app_date] => 2005-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2561 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20070070729.pdf [firstpage_image] =>[orig_patent_app_number] => 11217503 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/217503
High access speed flash controller Sep 1, 2005 Issued
Array ( [id] => 507416 [patent_doc_number] => 07206238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Integrated semiconductor memory comprising at least one word line and method' [patent_app_type] => utility [patent_app_number] => 11/218913 [patent_app_country] => US [patent_app_date] => 2005-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8801 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/206/07206238.pdf [firstpage_image] =>[orig_patent_app_number] => 11218913 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/218913
Integrated semiconductor memory comprising at least one word line and method Aug 31, 2005 Issued
Array ( [id] => 490092 [patent_doc_number] => 07218553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Method for programming memory cells including transconductance degradation detection' [patent_app_type] => utility [patent_app_number] => 11/215311 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 8941 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/218/07218553.pdf [firstpage_image] =>[orig_patent_app_number] => 11215311 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/215311
Method for programming memory cells including transconductance degradation detection Aug 29, 2005 Issued
Array ( [id] => 5709202 [patent_doc_number] => 20060050547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Resistive memory arrangement' [patent_app_type] => utility [patent_app_number] => 11/215443 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4119 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20060050547.pdf [firstpage_image] =>[orig_patent_app_number] => 11215443 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/215443
Resistive memory arrangement Aug 29, 2005 Issued
Array ( [id] => 5647445 [patent_doc_number] => 20060133177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'MOS semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/213877 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5806 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20060133177.pdf [firstpage_image] =>[orig_patent_app_number] => 11213877 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/213877
MOS semiconductor integrated circuit device Aug 29, 2005 Issued
Array ( [id] => 5714382 [patent_doc_number] => 20060077745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'Semiconductor device and method for boosting word line' [patent_app_type] => utility [patent_app_number] => 11/214633 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6284 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20060077745.pdf [firstpage_image] =>[orig_patent_app_number] => 11214633 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/214633
Semiconductor device and method for boosting word line Aug 29, 2005 Abandoned
Array ( [id] => 6930044 [patent_doc_number] => 20050281078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Method and system for data communication on a chip' [patent_app_type] => utility [patent_app_number] => 11/211986 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4648 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20050281078.pdf [firstpage_image] =>[orig_patent_app_number] => 11211986 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/211986
Method and system for data communication on a chip Aug 24, 2005 Issued
Array ( [id] => 553871 [patent_doc_number] => 07164595 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-16 [patent_title] => 'Device and method for using dynamic cell plate sensing in a DRAM memory cell' [patent_app_type] => utility [patent_app_number] => 11/212987 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7029 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/164/07164595.pdf [firstpage_image] =>[orig_patent_app_number] => 11212987 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212987
Device and method for using dynamic cell plate sensing in a DRAM memory cell Aug 24, 2005 Issued
Array ( [id] => 5147320 [patent_doc_number] => 20070047374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'MEMORY CONTROLLER AND MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/211861 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20070047374.pdf [firstpage_image] =>[orig_patent_app_number] => 11211861 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/211861
Memory controller and memory system Aug 24, 2005 Issued
Array ( [id] => 7602632 [patent_doc_number] => 07236404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Structures and methods for enhancing erase uniformity in an NROM array' [patent_app_type] => utility [patent_app_number] => 11/210425 [patent_app_country] => US [patent_app_date] => 2005-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4290 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/236/07236404.pdf [firstpage_image] =>[orig_patent_app_number] => 11210425 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/210425
Structures and methods for enhancing erase uniformity in an NROM array Aug 23, 2005 Issued
Array ( [id] => 531753 [patent_doc_number] => 07187606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-06 [patent_title] => 'Read port circuit for register file' [patent_app_type] => utility [patent_app_number] => 11/208911 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187606.pdf [firstpage_image] =>[orig_patent_app_number] => 11208911 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/208911
Read port circuit for register file Aug 21, 2005 Issued
Array ( [id] => 916524 [patent_doc_number] => 07327596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-05 [patent_title] => 'Electrostatic capacitance detection device and smart card' [patent_app_type] => utility [patent_app_number] => 11/207841 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8664 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 450 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/327/07327596.pdf [firstpage_image] =>[orig_patent_app_number] => 11207841 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207841
Electrostatic capacitance detection device and smart card Aug 21, 2005 Issued
Array ( [id] => 607938 [patent_doc_number] => 07154801 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-26 [patent_title] => 'Protection circuit of a memory module and the method thereof' [patent_app_type] => utility [patent_app_number] => 11/207789 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3527 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/154/07154801.pdf [firstpage_image] =>[orig_patent_app_number] => 11207789 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207789
Protection circuit of a memory module and the method thereof Aug 21, 2005 Issued
Array ( [id] => 728096 [patent_doc_number] => 07046547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Magnetic non-volatile memory coil layout architecture and process integration scheme' [patent_app_type] => utility [patent_app_number] => 11/204921 [patent_app_country] => US [patent_app_date] => 2005-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8479 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046547.pdf [firstpage_image] =>[orig_patent_app_number] => 11204921 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/204921
Magnetic non-volatile memory coil layout architecture and process integration scheme Aug 15, 2005 Issued
Array ( [id] => 494589 [patent_doc_number] => 07215583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-08 [patent_title] => 'Circuit for inhibition of program disturbance in memory devices' [patent_app_type] => utility [patent_app_number] => 11/204477 [patent_app_country] => US [patent_app_date] => 2005-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2911 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/215/07215583.pdf [firstpage_image] =>[orig_patent_app_number] => 11204477 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/204477
Circuit for inhibition of program disturbance in memory devices Aug 15, 2005 Issued
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