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Chun Kuan Lee

Examiner (ID: 2936, Phone: (571)272-0671 , Office: P/2181 )

Most Active Art Unit
2181
Art Unit(s)
2181
Total Applications
798
Issued Applications
495
Pending Applications
81
Abandoned Applications
248

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19391520 [patent_doc_number] => 20240281390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => MEMORY DEVICE WITH 4N AND 8N DIE STACKS [patent_app_type] => utility [patent_app_number] => 18/410808 [patent_app_country] => US [patent_app_date] => 2024-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18410808 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/410808
MEMORY DEVICE WITH 4N AND 8N DIE STACKS Jan 10, 2024 Pending
Array ( [id] => 19320285 [patent_doc_number] => 20240241829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => APPARATUS AND METHOD FOR CCIX INTERFACE BASED ON USE OF QoS FIELD [patent_app_type] => utility [patent_app_number] => 18/408642 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408642 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408642
APPARATUS AND METHOD FOR CCIX INTERFACE BASED ON USE OF QoS FIELD Jan 9, 2024 Pending
Array ( [id] => 19320285 [patent_doc_number] => 20240241829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => APPARATUS AND METHOD FOR CCIX INTERFACE BASED ON USE OF QoS FIELD [patent_app_type] => utility [patent_app_number] => 18/408642 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408642 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408642
APPARATUS AND METHOD FOR CCIX INTERFACE BASED ON USE OF QoS FIELD Jan 9, 2024 Pending
Array ( [id] => 20131037 [patent_doc_number] => 12373350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Cache-line retention hint information for conditional write instruction [patent_app_type] => utility [patent_app_number] => 18/394400 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9410 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18394400 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/394400
Cache-line retention hint information for conditional write instruction Dec 21, 2023 Issued
Array ( [id] => 19100816 [patent_doc_number] => 20240120044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => GATEWAY CONFORMANCE VALIDATION [patent_app_type] => utility [patent_app_number] => 18/544193 [patent_app_country] => US [patent_app_date] => 2023-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544193 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/544193
GATEWAY CONFORMANCE VALIDATION Dec 17, 2023 Pending
Array ( [id] => 20273773 [patent_doc_number] => 12443555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Frame alignment recovery for a high-speed signaling interconnect [patent_app_type] => utility [patent_app_number] => 18/538758 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538758 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/538758
Frame alignment recovery for a high-speed signaling interconnect Dec 12, 2023 Issued
Array ( [id] => 19383173 [patent_doc_number] => 20240273043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => MEMORY MANAGEMENT DEVICE AND METHOD APPLIED TO INTELLIGENCE PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 18/505362 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505362 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/505362
Memory management device and method applied to intelligence processing unit Nov 8, 2023 Issued
18/498853 CONSENSUS PROCESSING DEVICE FOR REDUCING LATENCY IN DISTRIBUTED SYSTEMS Oct 30, 2023 Abandoned
Array ( [id] => 20000603 [patent_doc_number] => 20250138825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => PREFETCHING PROGRAM CODE FROM FLASH MEMORY BASED ON BRANCH LOGIC [patent_app_type] => utility [patent_app_number] => 18/498423 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18498423 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/498423
PREFETCHING PROGRAM CODE FROM FLASH MEMORY BASED ON BRANCH LOGIC Oct 30, 2023 Pending
Array ( [id] => 19985753 [patent_doc_number] => 20250123975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => SYSTEMS AND METHODS FOR BUFFER MANAGEMENT DURING A DATABASE BACKUP [patent_app_type] => utility [patent_app_number] => 18/487510 [patent_app_country] => US [patent_app_date] => 2023-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18487510 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/487510
SYSTEMS AND METHODS FOR BUFFER MANAGEMENT DURING A DATABASE BACKUP Oct 15, 2023 Pending
Array ( [id] => 19949930 [patent_doc_number] => 12321292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Chip card socket communication [patent_app_type] => utility [patent_app_number] => 18/481983 [patent_app_country] => US [patent_app_date] => 2023-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4264 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18481983 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/481983
Chip card socket communication Oct 4, 2023 Issued
Array ( [id] => 19251004 [patent_doc_number] => 20240201994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => FLOW CONTROL METHOD, RECORDING MEDIUM, AND INFORMATION PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 18/375795 [patent_app_country] => US [patent_app_date] => 2023-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18375795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/375795
FLOW CONTROL METHOD, RECORDING MEDIUM, AND INFORMATION PROCESSING DEVICE Oct 1, 2023 Pending
18/476422 KV-CACHE STREAMING FOR IMPROVED PERFORMANCE AND FAULT TOLERANCE IN GENERATIVE MODEL SERVING Sep 27, 2023 Pending
Array ( [id] => 19872629 [patent_doc_number] => 12265489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Communicating data with stacked memory dies [patent_app_type] => utility [patent_app_number] => 18/369622 [patent_app_country] => US [patent_app_date] => 2023-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 39175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18369622 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/369622
Communicating data with stacked memory dies Sep 17, 2023 Issued
Array ( [id] => 19022022 [patent_doc_number] => 20240078193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => OUTPUT METHOD AND DEVICE [patent_app_type] => utility [patent_app_number] => 18/457842 [patent_app_country] => US [patent_app_date] => 2023-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18457842 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/457842
OUTPUT METHOD AND DEVICE Aug 28, 2023 Pending
Array ( [id] => 19950484 [patent_doc_number] => 12321849 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-03 [patent_title] => Performing hardware operator fusion [patent_app_type] => utility [patent_app_number] => 18/238722 [patent_app_country] => US [patent_app_date] => 2023-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12204 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18238722 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/238722
Performing hardware operator fusion Aug 27, 2023 Issued
Array ( [id] => 19819238 [patent_doc_number] => 20250077445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => CROSS-DOMAIN VOLTAGE BUS RESOURCE SHARING FOR IMPROVED POWER DELIVERY NETWORK [patent_app_type] => utility [patent_app_number] => 18/456981 [patent_app_country] => US [patent_app_date] => 2023-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18456981 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/456981
CROSS-DOMAIN VOLTAGE BUS RESOURCE SHARING FOR IMPROVED POWER DELIVERY NETWORK Aug 27, 2023 Pending
Array ( [id] => 19942594 [patent_doc_number] => 12314726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Performance benchmarking-based selection of processor for generating graphic primitives [patent_app_type] => utility [patent_app_number] => 18/457112 [patent_app_country] => US [patent_app_date] => 2023-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1107 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18457112 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/457112
Performance benchmarking-based selection of processor for generating graphic primitives Aug 27, 2023 Issued
Array ( [id] => 18847082 [patent_doc_number] => 20230409486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => FAULT BUFFER FOR TRACKING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/456420 [patent_app_country] => US [patent_app_date] => 2023-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18456420 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/456420
FAULT BUFFER FOR TRACKING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM Aug 24, 2023 Pending
Array ( [id] => 18847082 [patent_doc_number] => 20230409486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => FAULT BUFFER FOR TRACKING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/456420 [patent_app_country] => US [patent_app_date] => 2023-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18456420 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/456420
FAULT BUFFER FOR TRACKING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM Aug 24, 2023 Pending
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