Chun Kuan Lee

Array ( [id] => 18839002 [patent_doc_number] => 11847073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Data path interface circuit, memory and memory system [patent_app_type] => utility [patent_app_number] => 17/446571 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7448 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17293743 [patent_doc_number] => 20210389582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => ENDOSCOPE MOTHERBOARD, ENDOSCOPE AND DETECTION METHOD [patent_app_type] => utility [patent_app_number] => 17/446232 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17261100 [patent_doc_number] => 20210374085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => MODULAR SYSTEM ARCHITECTURE FOR SUPPORTING MULTIPLE SOLID-STATE DRIVES [patent_app_type] => utility [patent_app_number] => 17/405770 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18053068 [patent_doc_number] => 11526453 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-13 [patent_title] => Apparatus including parallel pipelines and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/401729 [patent_app_country] => US [patent_app_date] => 2021-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14711 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17484344 [patent_doc_number] => 20220091848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => SYSTEMS AND METHODS TO LOAD A TILE REGISTER PAIR [patent_app_type] => utility [patent_app_number] => 17/398927 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18197664 [patent_doc_number] => 20230051183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => APPARATUS INCLUDING RECONFIGURABLE INTERFACE AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/398863 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19062168 [patent_doc_number] => 11941404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Processor and method for controlling the processor [patent_app_type] => utility [patent_app_number] => 17/375574 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 15665 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17447367 [patent_doc_number] => 20220067872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => GRAPHICS PROCESSING UNIT INCLUDING DELEGATOR AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/372851 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17447367 [patent_doc_number] => 20220067872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => GRAPHICS PROCESSING UNIT INCLUDING DELEGATOR AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/372851 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18262177 [patent_doc_number] => 11609879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Techniques for configuring parallel processors for different application domains [patent_app_type] => utility [patent_app_number] => 17/365315 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 16581 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365315 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18925529 [patent_doc_number] => 20240028533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => AUTOMATED DESIGN OF BEHAVIORAL-BASED DATA MOVERS FOR FIELD PROGRAMMABLE GATE ARRAYS OR OTHER LOGIC DEVICES [patent_app_type] => utility [patent_app_number] => 17/364481 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17172611 [patent_doc_number] => 20210326281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => APPARATUS AND METHODS FOR IN DATA PATH COMPUTE OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/360388 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360388 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18095583 [patent_doc_number] => 20220413924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => USING SPARSITY METADATA TO REDUCE SYSTOLIC ARRAY POWER CONSUMPTION [patent_app_type] => utility [patent_app_number] => 17/358542 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 51858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18662492 [patent_doc_number] => 20230308514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => INPUT UNIT, CONTROL SYSTEM, COMMUNICATION METHOD, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 18/035517 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18035517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17597790 [patent_doc_number] => 20220147364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => SERVER BASEBOARD, SERVER, CONTROL METHOD, ELECTRONIC APPARATUS AND READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/338870 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17338870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17581708 [patent_doc_number] => 20220138563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => METHOD AND DEVICE WITH DEEP LEARNING OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/338102 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17338102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17098956 [patent_doc_number] => 20210286747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => SYSTEMS AND METHODS FOR SUPPORTING INTER-CHASSIS MANAGEABILITY OF NVME OVER FABRICS BASED SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/336877 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17336877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18038340 [patent_doc_number] => 20220382556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => METHOD AND APPARATUS FOR A LOGIC-BASED FILTER ENGINE [patent_app_type] => utility [patent_app_number] => 17/331237 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19294890 [patent_doc_number] => 12034256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Systems, devices, and methods for connectors [patent_app_type] => utility [patent_app_number] => 17/329559 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4024 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17329559 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19719367 [patent_doc_number] => 12204906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Profiling of sampled operations processed by processing circuitry [patent_app_type] => utility [patent_app_number] => 17/999167 [patent_app_country] => US [patent_app_date] => 2021-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 19135 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17999167 [rel_patent_id] =>[rel_patent_doc_number] =>)