Search

Chuong A. Luu

Examiner (ID: 3640, Phone: (571)272-1902 , Office: P/2898 )

Most Active Art Unit
2898
Art Unit(s)
2825, 2898, 2892, 2818
Total Applications
2166
Issued Applications
1978
Pending Applications
24
Abandoned Applications
175

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16896487 [patent_doc_number] => 11038050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/990423 [patent_app_country] => US [patent_app_date] => 2020-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 35 [patent_no_of_words] => 12691 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16990423 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/990423
Semiconductor device and method of manufacturing the same Aug 10, 2020 Issued
Array ( [id] => 18387274 [patent_doc_number] => 11658067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Semiconductor structure and formation method thereof [patent_app_type] => utility [patent_app_number] => 16/989299 [patent_app_country] => US [patent_app_date] => 2020-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6097 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16989299 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/989299
Semiconductor structure and formation method thereof Aug 9, 2020 Issued
Array ( [id] => 17295423 [patent_doc_number] => 20210391262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/945437 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16945437 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/945437
Semiconductor device Jul 30, 2020 Issued
Array ( [id] => 17389339 [patent_doc_number] => 20220037191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/944018 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16944018 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/944018
Semiconductor device structure and methods of forming the same Jul 29, 2020 Issued
Array ( [id] => 18032077 [patent_doc_number] => 11515275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Copper wire bond on gold bump on semiconductor die bond pad [patent_app_type] => utility [patent_app_number] => 16/941701 [patent_app_country] => US [patent_app_date] => 2020-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5900 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941701 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/941701
Copper wire bond on gold bump on semiconductor die bond pad Jul 28, 2020 Issued
Array ( [id] => 17456238 [patent_doc_number] => 11271105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/940671 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4039 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16940671 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/940671
Semiconductor device Jul 27, 2020 Issued
Array ( [id] => 17254024 [patent_doc_number] => 11189522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/939391 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 56 [patent_no_of_words] => 10199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939391 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/939391
Semiconductor device and method of manufacturing the same Jul 26, 2020 Issued
Array ( [id] => 17818717 [patent_doc_number] => 11424341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/937901 [patent_app_country] => US [patent_app_date] => 2020-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 9829 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937901 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/937901
Semiconductor device Jul 23, 2020 Issued
Array ( [id] => 17332363 [patent_doc_number] => 11222831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Stacked integrated circuit devices [patent_app_type] => utility [patent_app_number] => 16/947241 [patent_app_country] => US [patent_app_date] => 2020-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16947241 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/947241
Stacked integrated circuit devices Jul 23, 2020 Issued
Array ( [id] => 17366103 [patent_doc_number] => 11233136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Silicon carbide oxide hard mask for reducing dishing effects [patent_app_type] => utility [patent_app_number] => 16/937252 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937252 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/937252
Silicon carbide oxide hard mask for reducing dishing effects Jul 22, 2020 Issued
Array ( [id] => 16601575 [patent_doc_number] => 20210028106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => METHOD OF FORMING A MULTI-LEVEL INTERCONNECT STRUCTURE IN A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/936271 [patent_app_country] => US [patent_app_date] => 2020-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936271 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/936271
Method of forming a multi-level interconnect structure in a semiconductor device Jul 21, 2020 Issued
Array ( [id] => 16425207 [patent_doc_number] => 20200350405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => EXTENDED DRAIN MOS WITH DUAL WELL ISOLATION [patent_app_type] => utility [patent_app_number] => 16/931935 [patent_app_country] => US [patent_app_date] => 2020-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16931935 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/931935
Extended drain MOS with dual well isolation Jul 16, 2020 Issued
Array ( [id] => 17359835 [patent_doc_number] => 20220020631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 16/930913 [patent_app_country] => US [patent_app_date] => 2020-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16930913 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/930913
Integrated circuit structure and method for preparing the same Jul 15, 2020 Issued
Array ( [id] => 17347121 [patent_doc_number] => 20220013452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/925254 [patent_app_country] => US [patent_app_date] => 2020-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16925254 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/925254
Semiconductor device package and method of manufacturing the same Jul 8, 2020 Issued
Array ( [id] => 16920719 [patent_doc_number] => 20210193811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/923514 [patent_app_country] => US [patent_app_date] => 2020-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16923514 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/923514
Electronic device and method of manufacturing the same Jul 7, 2020 Issued
Array ( [id] => 17289161 [patent_doc_number] => 11205722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Lateral DMOS having reduced lateral size [patent_app_type] => utility [patent_app_number] => 16/922157 [patent_app_country] => US [patent_app_date] => 2020-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5161 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16922157 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/922157
Lateral DMOS having reduced lateral size Jul 6, 2020 Issued
Array ( [id] => 16677685 [patent_doc_number] => 20210066451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => HIGH VOLTAGE DEVICE WITH GATE EXTENSIONS [patent_app_type] => utility [patent_app_number] => 16/921075 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921075 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/921075
High voltage device with gate extensions Jul 5, 2020 Issued
Array ( [id] => 16456167 [patent_doc_number] => 20200365593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING A PLURALITY THEREOF [patent_app_type] => utility [patent_app_number] => 16/920427 [patent_app_country] => US [patent_app_date] => 2020-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16920427 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/920427
Semiconductor structure and method for manufacturing a plurality thereof Jul 2, 2020 Issued
Array ( [id] => 17318944 [patent_doc_number] => 20210407994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/915930 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11156 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915930 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/915930
Semiconductor device structure and methods of forming the same Jun 28, 2020 Issued
Array ( [id] => 16545017 [patent_doc_number] => 20200411432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => WIRING SUBSTRATE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/910239 [patent_app_country] => US [patent_app_date] => 2020-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16910239 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/910239
Wiring substrate and manufacturing method thereof Jun 23, 2020 Issued
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