Search

Chuong D. Ngo

Examiner (ID: 8858, Phone: (571)272-3731 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2787, 2306, 2121, 2899, 2124, 2182, 2183, 2193
Total Applications
2158
Issued Applications
1754
Pending Applications
68
Abandoned Applications
343

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11019992 [patent_doc_number] => 20160216945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'HARDWARE NON-DETERMINISTIC RANDOM BYTE GENERATOR' [patent_app_type] => utility [patent_app_number] => 15/006991 [patent_app_country] => US [patent_app_date] => 2016-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4256 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15006991 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/006991
Hardware non-deterministic random byte generator Jan 25, 2016 Issued
Array ( [id] => 11830567 [patent_doc_number] => 09727309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Computer-readable recording medium, encoding apparatus, and encoding method' [patent_app_type] => utility [patent_app_number] => 14/995640 [patent_app_country] => US [patent_app_date] => 2016-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 15185 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14995640 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/995640
Computer-readable recording medium, encoding apparatus, and encoding method Jan 13, 2016 Issued
Array ( [id] => 11910096 [patent_doc_number] => 09778905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-03 [patent_title] => 'Multiplier circuits configurable for real or complex operation' [patent_app_type] => utility [patent_app_number] => 14/995100 [patent_app_country] => US [patent_app_date] => 2016-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13416 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14995100 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/995100
Multiplier circuits configurable for real or complex operation Jan 12, 2016 Issued
Array ( [id] => 16263185 [patent_doc_number] => 10754617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Generating of random numbers [patent_app_type] => utility [patent_app_number] => 14/994367 [patent_app_country] => US [patent_app_date] => 2016-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4045 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14994367 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/994367
Generating of random numbers Jan 12, 2016 Issued
Array ( [id] => 13831235 [patent_doc_number] => 20190019102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => QUANTUM PHASE ESTIMATION OF MULTIPLE EIGENVALUES [patent_app_type] => utility [patent_app_number] => 16/067428 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16067428 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/067428
Quantum phase estimation of multiple eigenvalues Dec 29, 2015 Issued
Array ( [id] => 11708847 [patent_doc_number] => 20170177347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Instruction and Logic for Detecting the Floating Point Cancellation Effect' [patent_app_type] => utility [patent_app_number] => 14/975811 [patent_app_country] => US [patent_app_date] => 2015-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 22291 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14975811 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/975811
Instruction and logic for detecting the floating point cancellation effect Dec 19, 2015 Issued
Array ( [id] => 10982527 [patent_doc_number] => 20160179471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'MINIMIZING PROCESSING LOAD WHEN SOLVING MAXIMUM SATISFIABILITY PROBLEM' [patent_app_type] => utility [patent_app_number] => 14/974330 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14974330 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/974330
MINIMIZING PROCESSING LOAD WHEN SOLVING MAXIMUM SATISFIABILITY PROBLEM Dec 17, 2015 Abandoned
Array ( [id] => 13948365 [patent_doc_number] => 10209957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Partial remainder/divisor table split implementation [patent_app_type] => utility [patent_app_number] => 14/972077 [patent_app_country] => US [patent_app_date] => 2015-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8412 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14972077 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/972077
Partial remainder/divisor table split implementation Dec 15, 2015 Issued
Array ( [id] => 10826954 [patent_doc_number] => 20160173124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'SYSTEM AND METHOD OF COMBINATORIAL HYPERMAP BASED DATA REPRESENTATIONS AND OPERATIONS' [patent_app_type] => utility [patent_app_number] => 14/965708 [patent_app_country] => US [patent_app_date] => 2015-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14461 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14965708 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/965708
System and method of combinatorial hypermap based data representations and operations Dec 9, 2015 Issued
Array ( [id] => 14330545 [patent_doc_number] => 10296290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Digital signal processor [patent_app_type] => utility [patent_app_number] => 14/964817 [patent_app_country] => US [patent_app_date] => 2015-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7773 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14964817 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/964817
Digital signal processor Dec 9, 2015 Issued
Array ( [id] => 11006155 [patent_doc_number] => 20160203105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/958247 [patent_app_country] => US [patent_app_date] => 2015-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 20503 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14958247 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/958247
INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM Dec 2, 2015 Abandoned
Array ( [id] => 11410851 [patent_doc_number] => 09558156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-31 [patent_title] => 'Sparse matrix multiplication using a single field programmable gate array module' [patent_app_type] => utility [patent_app_number] => 14/949937 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9395 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14949937 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/949937
Sparse matrix multiplication using a single field programmable gate array module Nov 23, 2015 Issued
Array ( [id] => 10991581 [patent_doc_number] => 20160188526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'ELECTRONIC DEVICE, DISPLAY METHOD AT TIME OF EXECUTION OF VERIFICATION WITH ELECTRONIC DEVICE, AND STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 14/948719 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4183 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14948719 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/948719
Electronic device, display method at time of execution of verification with electronic device, and storage medium Nov 22, 2015 Issued
Array ( [id] => 11629485 [patent_doc_number] => 20170139673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'REDUNDANT REPRESENTATION OF NUMERIC VALUE USING OVERLAP BITS' [patent_app_type] => utility [patent_app_number] => 14/939175 [patent_app_country] => US [patent_app_date] => 2015-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 41887 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14939175 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/939175
Redundant representation of numeric value using overlap bits Nov 11, 2015 Issued
Array ( [id] => 11846346 [patent_doc_number] => 09733899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Lane position information for processing of vector' [patent_app_type] => utility [patent_app_number] => 14/939371 [patent_app_country] => US [patent_app_date] => 2015-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 39 [patent_no_of_words] => 45645 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14939371 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/939371
Lane position information for processing of vector Nov 11, 2015 Issued
Array ( [id] => 11724110 [patent_doc_number] => 09696965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'Input-dependent random number generation using memory arrays' [patent_app_type] => utility [patent_app_number] => 14/938861 [patent_app_country] => US [patent_app_date] => 2015-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5193 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14938861 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/938861
Input-dependent random number generation using memory arrays Nov 11, 2015 Issued
Array ( [id] => 12255889 [patent_doc_number] => 09928031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Overlap propagation operation' [patent_app_type] => utility [patent_app_number] => 14/939301 [patent_app_country] => US [patent_app_date] => 2015-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 39 [patent_no_of_words] => 41793 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14939301 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/939301
Overlap propagation operation Nov 11, 2015 Issued
Array ( [id] => 10786139 [patent_doc_number] => 20160132295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'EFFICIENT IMPLEMENTATION OF A MULTIPLIER/ACCUMULATOR WITH LOAD' [patent_app_type] => utility [patent_app_number] => 14/938046 [patent_app_country] => US [patent_app_date] => 2015-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1499 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14938046 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/938046
Efficient implementation of a multiplier/accumulator with load Nov 10, 2015 Issued
Array ( [id] => 10786304 [patent_doc_number] => 20160132461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'HIGH PERFORMANCE IMPLEMENTATION OF THE FFT BUTTERFLY COMPUTATION' [patent_app_type] => utility [patent_app_number] => 14/938017 [patent_app_country] => US [patent_app_date] => 2015-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1893 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14938017 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/938017
High performance implementation of the FFT butterfly computation Nov 10, 2015 Issued
Array ( [id] => 12088216 [patent_doc_number] => 09841946 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-12 [patent_title] => 'Method and apparatus for modulo operation' [patent_app_type] => utility [patent_app_number] => 14/938053 [patent_app_country] => US [patent_app_date] => 2015-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3617 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14938053 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/938053
Method and apparatus for modulo operation Nov 10, 2015 Issued
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