Search

Chuong D. Ngo

Examiner (ID: 8858, Phone: (571)272-3731 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2787, 2306, 2121, 2899, 2124, 2182, 2183, 2193
Total Applications
2158
Issued Applications
1754
Pending Applications
68
Abandoned Applications
343

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5860760 [patent_doc_number] => 20060229747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Driver for a function unit parametrized by a number of input variables' [patent_app_type] => utility [patent_app_number] => 11/376242 [patent_app_country] => US [patent_app_date] => 2006-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4368 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20060229747.pdf [firstpage_image] =>[orig_patent_app_number] => 11376242 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/376242
Driver for a function unit parametrized by a number of input variables Mar 15, 2006 Issued
Array ( [id] => 4555009 [patent_doc_number] => 07890563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Multi-channel sample rate conversion method' [patent_app_type] => utility [patent_app_number] => 11/375874 [patent_app_country] => US [patent_app_date] => 2006-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3570 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/890/07890563.pdf [firstpage_image] =>[orig_patent_app_number] => 11375874 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/375874
Multi-channel sample rate conversion method Mar 13, 2006 Issued
Array ( [id] => 7681233 [patent_doc_number] => 20100023575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'PREDICTOR' [patent_app_type] => utility [patent_app_number] => 11/908300 [patent_app_country] => US [patent_app_date] => 2006-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2737 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20100023575.pdf [firstpage_image] =>[orig_patent_app_number] => 11908300 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/908300
PREDICTOR Mar 8, 2006 Abandoned
Array ( [id] => 5260572 [patent_doc_number] => 20070214204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Negative two\'s complement numbering system' [patent_app_type] => utility [patent_app_number] => 11/370783 [patent_app_country] => US [patent_app_date] => 2006-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3419 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20070214204.pdf [firstpage_image] =>[orig_patent_app_number] => 11370783 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/370783
Negative two's complement numbering system Mar 7, 2006 Abandoned
Array ( [id] => 8254489 [patent_doc_number] => 20120158808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'METHOD FOR OPTIMIZATION OF MEASUREMENT STANDARD AND INDUSTRIAL ENGINEERING CALCULATION METHOD USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/280344 [patent_app_country] => US [patent_app_date] => 2006-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 27835 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20120158808.pdf [firstpage_image] =>[orig_patent_app_number] => 12280344 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/280344
METHOD FOR OPTIMIZATION OF MEASUREMENT STANDARD AND INDUSTRIAL ENGINEERING CALCULATION METHOD USING THE SAME Feb 26, 2006 Abandoned
Array ( [id] => 9169586 [patent_doc_number] => 08595279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Floating-point processor with reduced power requirements for selectable subprecision' [patent_app_type] => utility [patent_app_number] => 11/363118 [patent_app_country] => US [patent_app_date] => 2006-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4488 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11363118 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/363118
Floating-point processor with reduced power requirements for selectable subprecision Feb 26, 2006 Issued
Array ( [id] => 6262035 [patent_doc_number] => 20100030836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'Adder, Synthesis Device Thereof, Synthesis Method, Synthesis Program, and Synthesis Program Storage Medium' [patent_app_type] => utility [patent_app_number] => 11/884278 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8956 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20100030836.pdf [firstpage_image] =>[orig_patent_app_number] => 11884278 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/884278
Adder, Synthesis Device Thereof, Synthesis Method, Synthesis Program, and Synthesis Program Storage Medium Feb 15, 2006 Abandoned
Array ( [id] => 5071294 [patent_doc_number] => 20070192396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Packed add-subtract operation in a microprocessor' [patent_app_type] => utility [patent_app_number] => 11/352711 [patent_app_country] => US [patent_app_date] => 2006-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3784 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20070192396.pdf [firstpage_image] =>[orig_patent_app_number] => 11352711 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/352711
Packed add-subtract operation in a microprocessor Feb 12, 2006 Issued
Array ( [id] => 17249 [patent_doc_number] => 07805477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'Computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC audio decoding algorithm on programmable processors' [patent_app_type] => utility [patent_app_number] => 11/342765 [patent_app_country] => US [patent_app_date] => 2006-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5021 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/805/07805477.pdf [firstpage_image] =>[orig_patent_app_number] => 11342765 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/342765
Computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC audio decoding algorithm on programmable processors Jan 29, 2006 Issued
Array ( [id] => 27057 [patent_doc_number] => 07801939 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-21 [patent_title] => 'Complex and hypercomplex inclusive interval expression evaluations with stable numeric evaluations and precision efficacy testing' [patent_app_type] => utility [patent_app_number] => 11/336166 [patent_app_country] => US [patent_app_date] => 2006-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11850 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 900 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/801/07801939.pdf [firstpage_image] =>[orig_patent_app_number] => 11336166 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/336166
Complex and hypercomplex inclusive interval expression evaluations with stable numeric evaluations and precision efficacy testing Jan 18, 2006 Issued
Array ( [id] => 17264 [patent_doc_number] => 07805481 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-28 [patent_title] => 'Exploitation of topological categorization of chaotic and fractal functions, including field line calculations' [patent_app_type] => utility [patent_app_number] => 11/336187 [patent_app_country] => US [patent_app_date] => 2006-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 41722 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/805/07805481.pdf [firstpage_image] =>[orig_patent_app_number] => 11336187 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/336187
Exploitation of topological categorization of chaotic and fractal functions, including field line calculations Jan 18, 2006 Issued
Array ( [id] => 5613243 [patent_doc_number] => 20060115171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Apparatus and method for conversion into a transformed representation or for inverse conversion of the transformed representation' [patent_app_type] => utility [patent_app_number] => 11/331551 [patent_app_country] => US [patent_app_date] => 2006-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13421 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20060115171.pdf [firstpage_image] =>[orig_patent_app_number] => 11331551 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/331551
Apparatus and method for conversion into a transformed representation or for inverse conversion of the transformed representation Jan 12, 2006 Issued
Array ( [id] => 5178950 [patent_doc_number] => 20070180010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'System and method for iteratively eliminating common subexpressions in an arithmetic system' [patent_app_type] => utility [patent_app_number] => 11/331895 [patent_app_country] => US [patent_app_date] => 2006-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 9122 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20070180010.pdf [firstpage_image] =>[orig_patent_app_number] => 11331895 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/331895
System and method for iteratively eliminating common subexpressions in an arithmetic system Jan 12, 2006 Abandoned
Array ( [id] => 5644032 [patent_doc_number] => 20060282487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'Method and system for pipelining saturated accumulation and other loops with loop-carried dependencies' [patent_app_type] => utility [patent_app_number] => 11/331830 [patent_app_country] => US [patent_app_date] => 2006-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6464 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20060282487.pdf [firstpage_image] =>[orig_patent_app_number] => 11331830 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/331830
Method and system for pipelining saturated accumulation and other loops with loop-carried dependencies Jan 11, 2006 Issued
Array ( [id] => 4585163 [patent_doc_number] => 07856467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-21 [patent_title] => 'Integrated circuit including at least one configurable logic cell capable of multiplication' [patent_app_type] => utility [patent_app_number] => 11/324019 [patent_app_country] => US [patent_app_date] => 2005-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3033 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/856/07856467.pdf [firstpage_image] =>[orig_patent_app_number] => 11324019 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/324019
Integrated circuit including at least one configurable logic cell capable of multiplication Dec 28, 2005 Issued
Array ( [id] => 4606235 [patent_doc_number] => 07987220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Computing filter coefficients for an equalizer in a communication receiver' [patent_app_type] => utility [patent_app_number] => 11/666609 [patent_app_country] => US [patent_app_date] => 2005-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3578 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 580 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/987/07987220.pdf [firstpage_image] =>[orig_patent_app_number] => 11666609 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/666609
Computing filter coefficients for an equalizer in a communication receiver Dec 19, 2005 Issued
Array ( [id] => 4442832 [patent_doc_number] => 07899859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Efficient error-check and exact-check for Newton-Raphson divide and square-root operations' [patent_app_type] => utility [patent_app_number] => 11/314639 [patent_app_country] => US [patent_app_date] => 2005-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4515 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/899/07899859.pdf [firstpage_image] =>[orig_patent_app_number] => 11314639 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/314639
Efficient error-check and exact-check for Newton-Raphson divide and square-root operations Dec 19, 2005 Issued
Array ( [id] => 4547433 [patent_doc_number] => 07925686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Linear transformation circuit' [patent_app_type] => utility [patent_app_number] => 11/311971 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11379 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/925/07925686.pdf [firstpage_image] =>[orig_patent_app_number] => 11311971 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/311971
Linear transformation circuit Dec 18, 2005 Issued
Array ( [id] => 4507233 [patent_doc_number] => 07958178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Finite impulse response filter for a time-synchronized system' [patent_app_type] => utility [patent_app_number] => 11/298246 [patent_app_country] => US [patent_app_date] => 2005-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3313 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958178.pdf [firstpage_image] =>[orig_patent_app_number] => 11298246 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/298246
Finite impulse response filter for a time-synchronized system Dec 8, 2005 Issued
Array ( [id] => 4461877 [patent_doc_number] => 07895255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Method and apparatus for performing a multiplication or division operation in an electronic circuit' [patent_app_type] => utility [patent_app_number] => 11/289835 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5810 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/895/07895255.pdf [firstpage_image] =>[orig_patent_app_number] => 11289835 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/289835
Method and apparatus for performing a multiplication or division operation in an electronic circuit Nov 29, 2005 Issued
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