Search

Chuong D. Ngo

Examiner (ID: 8858, Phone: (571)272-3731 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2787, 2306, 2121, 2899, 2124, 2182, 2183, 2193
Total Applications
2158
Issued Applications
1754
Pending Applications
68
Abandoned Applications
343

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5907556 [patent_doc_number] => 20060048122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Method, system and computer program product for hierarchical loop optimization of machine executable code' [patent_app_type] => utility [patent_app_number] => 10/929175 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10272 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20060048122.pdf [firstpage_image] =>[orig_patent_app_number] => 10929175 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/929175
Method, system and computer program product for hierarchical loop optimization of machine executable code Aug 29, 2004 Abandoned
10/920879 Math coprocessor Aug 17, 2004 Abandoned
Array ( [id] => 7091570 [patent_doc_number] => 20050010626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Selectable quantization in an encoder' [patent_app_type] => utility [patent_app_number] => 10/917005 [patent_app_country] => US [patent_app_date] => 2004-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6426 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20050010626.pdf [firstpage_image] =>[orig_patent_app_number] => 10917005 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/917005
Selectable quantization in an encoder Aug 11, 2004 Issued
Array ( [id] => 86327 [patent_doc_number] => 07747666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-29 [patent_title] => 'Parallel filter realization for wideband programmable digital radios' [patent_app_type] => utility [patent_app_number] => 10/914554 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 12801 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/747/07747666.pdf [firstpage_image] =>[orig_patent_app_number] => 10914554 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/914554
Parallel filter realization for wideband programmable digital radios Aug 8, 2004 Issued
Array ( [id] => 5882190 [patent_doc_number] => 20060031273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Tunable multi-phase-offset direct digital synthesizer' [patent_app_type] => utility [patent_app_number] => 10/914046 [patent_app_country] => US [patent_app_date] => 2004-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2900 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20060031273.pdf [firstpage_image] =>[orig_patent_app_number] => 10914046 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/914046
Tunable multi-phase-offset direct digital synthesizer Aug 5, 2004 Issued
Array ( [id] => 5882189 [patent_doc_number] => 20060031272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Alignment shifter supporting multiple precisions' [patent_app_type] => utility [patent_app_number] => 10/912480 [patent_app_country] => US [patent_app_date] => 2004-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3699 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20060031272.pdf [firstpage_image] =>[orig_patent_app_number] => 10912480 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/912480
Alignment shifter supporting multiple precisions Aug 4, 2004 Abandoned
Array ( [id] => 580064 [patent_doc_number] => 07472152 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-30 [patent_title] => 'Accommodating fourier transformation attenuation between transform term frequencies' [patent_app_type] => utility [patent_app_number] => 10/914712 [patent_app_country] => US [patent_app_date] => 2004-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6292 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/472/07472152.pdf [firstpage_image] =>[orig_patent_app_number] => 10914712 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/914712
Accommodating fourier transformation attenuation between transform term frequencies Aug 1, 2004 Issued
Array ( [id] => 5821910 [patent_doc_number] => 20060026223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Apparatus and method for reducing the latency of sum-addressed shifters' [patent_app_type] => utility [patent_app_number] => 10/902475 [patent_app_country] => US [patent_app_date] => 2004-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3031 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20060026223.pdf [firstpage_image] =>[orig_patent_app_number] => 10902475 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/902475
Apparatus and method for reducing the latency of sum-addressed shifters Jul 28, 2004 Issued
Array ( [id] => 863799 [patent_doc_number] => 07373368 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-13 [patent_title] => 'Multiply execution unit that includes 4:2 and/or 5:3 compressors for performing integer and XOR multiplication' [patent_app_type] => utility [patent_app_number] => 10/891978 [patent_app_country] => US [patent_app_date] => 2004-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 6027 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/373/07373368.pdf [firstpage_image] =>[orig_patent_app_number] => 10891978 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/891978
Multiply execution unit that includes 4:2 and/or 5:3 compressors for performing integer and XOR multiplication Jul 14, 2004 Issued
Array ( [id] => 5794868 [patent_doc_number] => 20060015549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Method and apparatus for generation of gaussian deviates' [patent_app_type] => utility [patent_app_number] => 10/889676 [patent_app_country] => US [patent_app_date] => 2004-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2542 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20060015549.pdf [firstpage_image] =>[orig_patent_app_number] => 10889676 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889676
Method and apparatus for generation of gaussian deviates Jul 12, 2004 Abandoned
Array ( [id] => 7023363 [patent_doc_number] => 20050017757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Logical operation circuit and logical operation device' [patent_app_type] => utility [patent_app_number] => 10/889402 [patent_app_country] => US [patent_app_date] => 2004-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11392 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20050017757.pdf [firstpage_image] =>[orig_patent_app_number] => 10889402 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889402
Logical operation circuit and logical operation device Jul 11, 2004 Issued
Array ( [id] => 5739790 [patent_doc_number] => 20060010181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Multi-dimensional transpose for distributed memory network' [patent_app_type] => utility [patent_app_number] => 10/887026 [patent_app_country] => US [patent_app_date] => 2004-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5402 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20060010181.pdf [firstpage_image] =>[orig_patent_app_number] => 10887026 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/887026
Multi-dimensional transform for distributed memory network Jul 7, 2004 Issued
Array ( [id] => 9129986 [patent_doc_number] => 08577942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'Electronic device and data processing device for implementing cryptographic algorithms' [patent_app_type] => utility [patent_app_number] => 11/629358 [patent_app_country] => US [patent_app_date] => 2004-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 32 [patent_no_of_words] => 12900 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11629358 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/629358
Electronic device and data processing device for implementing cryptographic algorithms Jul 6, 2004 Issued
Array ( [id] => 5739791 [patent_doc_number] => 20060010182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Quantum random number generator' [patent_app_type] => utility [patent_app_number] => 10/885503 [patent_app_country] => US [patent_app_date] => 2004-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4116 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20060010182.pdf [firstpage_image] =>[orig_patent_app_number] => 10885503 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/885503
Quantum random number generator Jul 5, 2004 Abandoned
Array ( [id] => 592416 [patent_doc_number] => 07461113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Reduced complexity adaptive filter' [patent_app_type] => utility [patent_app_number] => 10/867140 [patent_app_country] => US [patent_app_date] => 2004-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2210 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/461/07461113.pdf [firstpage_image] =>[orig_patent_app_number] => 10867140 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/867140
Reduced complexity adaptive filter Jun 13, 2004 Issued
Array ( [id] => 7087960 [patent_doc_number] => 20050008072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Analog data compression' [patent_app_type] => utility [patent_app_number] => 10/863120 [patent_app_country] => US [patent_app_date] => 2004-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4415 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20050008072.pdf [firstpage_image] =>[orig_patent_app_number] => 10863120 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/863120
Analog data compression Jun 7, 2004 Issued
Array ( [id] => 7357680 [patent_doc_number] => 20040249877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Fast integer division with minimum number of iterations in substraction-based hardware divide processor' [patent_app_type] => new [patent_app_number] => 10/861152 [patent_app_country] => US [patent_app_date] => 2004-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2189 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20040249877.pdf [firstpage_image] =>[orig_patent_app_number] => 10861152 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/861152
Fast integer division with minimum number of iterations in substraction-based hardware divide processor Jun 3, 2004 Abandoned
Array ( [id] => 598478 [patent_doc_number] => 07444366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Faster shift value calculation using modified carry-lookahead adder' [patent_app_type] => utility [patent_app_number] => 10/853518 [patent_app_country] => US [patent_app_date] => 2004-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4427 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/444/07444366.pdf [firstpage_image] =>[orig_patent_app_number] => 10853518 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/853518
Faster shift value calculation using modified carry-lookahead adder May 25, 2004 Issued
Array ( [id] => 595389 [patent_doc_number] => 07454454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Method and apparatus for efficient calculation of a matrix power series' [patent_app_type] => utility [patent_app_number] => 10/851585 [patent_app_country] => US [patent_app_date] => 2004-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3498 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/454/07454454.pdf [firstpage_image] =>[orig_patent_app_number] => 10851585 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/851585
Method and apparatus for efficient calculation of a matrix power series May 20, 2004 Issued
Array ( [id] => 241254 [patent_doc_number] => 07593978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Processor reduction unit for accumulation of multiple operands with or without saturation' [patent_app_type] => utility [patent_app_number] => 10/841261 [patent_app_country] => US [patent_app_date] => 2004-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5392 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/593/07593978.pdf [firstpage_image] =>[orig_patent_app_number] => 10841261 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/841261
Processor reduction unit for accumulation of multiple operands with or without saturation May 6, 2004 Issued
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