Search

Chuong D. Ngo

Examiner (ID: 8858, Phone: (571)272-3731 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2787, 2306, 2121, 2899, 2124, 2182, 2183, 2193
Total Applications
2158
Issued Applications
1754
Pending Applications
68
Abandoned Applications
343

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 965601 [patent_doc_number] => 06950840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-27 [patent_title] => 'Noise invariant circuits, systems and methods' [patent_app_type] => utility [patent_app_number] => 10/832141 [patent_app_country] => US [patent_app_date] => 2004-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2596 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/950/06950840.pdf [firstpage_image] =>[orig_patent_app_number] => 10832141 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/832141
Noise invariant circuits, systems and methods Apr 25, 2004 Issued
Array ( [id] => 297732 [patent_doc_number] => 07543011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Montgomery modular multiplier and method thereof using carry save addition' [patent_app_type] => utility [patent_app_number] => 10/830041 [patent_app_country] => US [patent_app_date] => 2004-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8236 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/543/07543011.pdf [firstpage_image] =>[orig_patent_app_number] => 10830041 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/830041
Montgomery modular multiplier and method thereof using carry save addition Apr 22, 2004 Issued
Array ( [id] => 7352939 [patent_doc_number] => 20040193841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Matrix processing device in SMP node distributed memory type parallel computer' [patent_app_type] => new [patent_app_number] => 10/798287 [patent_app_country] => US [patent_app_date] => 2004-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 9515 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20040193841.pdf [firstpage_image] =>[orig_patent_app_number] => 10798287 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/798287
Matrix processing device in SMP node distributed memory type parallel computer Mar 11, 2004 Abandoned
Array ( [id] => 6992258 [patent_doc_number] => 20050091295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Apparatus for fractional RF signal synthesis with phase modulation' [patent_app_type] => utility [patent_app_number] => 10/796415 [patent_app_country] => US [patent_app_date] => 2004-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5285 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20050091295.pdf [firstpage_image] =>[orig_patent_app_number] => 10796415 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/796415
Apparatus for fractional RF signal synthesis with phase modulation Mar 9, 2004 Issued
Array ( [id] => 6946040 [patent_doc_number] => 20050198089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Mixed-scaling-rotation CORDIC method with scaling-free rotational operations for vector rotation' [patent_app_type] => utility [patent_app_number] => 10/793920 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2604 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20050198089.pdf [firstpage_image] =>[orig_patent_app_number] => 10793920 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/793920
Mixed-scaling-rotation CORDIC method with scaling-free rotational operations for vector rotation Mar 7, 2004 Abandoned
Array ( [id] => 580075 [patent_doc_number] => 07472153 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-30 [patent_title] => 'Method for exploiting bias in factor analysis using constrained alternating least squares algorithms' [patent_app_type] => utility [patent_app_number] => 10/794538 [patent_app_country] => US [patent_app_date] => 2004-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7591 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/472/07472153.pdf [firstpage_image] =>[orig_patent_app_number] => 10794538 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/794538
Method for exploiting bias in factor analysis using constrained alternating least squares algorithms Mar 3, 2004 Issued
Array ( [id] => 7277365 [patent_doc_number] => 20040236816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Carry look-ahead circuit and adder using same' [patent_app_type] => new [patent_app_number] => 10/791939 [patent_app_country] => US [patent_app_date] => 2004-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 22285 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20040236816.pdf [firstpage_image] =>[orig_patent_app_number] => 10791939 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/791939
Carry look-ahead circuit and adder using same Mar 1, 2004 Issued
Array ( [id] => 5245572 [patent_doc_number] => 20070241806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'Fast Filtering Means and Filtering and Decimation Methos' [patent_app_type] => utility [patent_app_number] => 10/591197 [patent_app_country] => US [patent_app_date] => 2004-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 14930 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20070241806.pdf [firstpage_image] =>[orig_patent_app_number] => 10591197 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/591197
Fast filtering means and filtering and decimation methods Mar 1, 2004 Issued
Array ( [id] => 7473832 [patent_doc_number] => 20040167953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Multi-function floating point arithmetic pipeline' [patent_app_type] => new [patent_app_number] => 10/786332 [patent_app_country] => US [patent_app_date] => 2004-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11080 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20040167953.pdf [firstpage_image] =>[orig_patent_app_number] => 10786332 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/786332
Multi-function floating point arithmetic pipeline Feb 25, 2004 Issued
Array ( [id] => 7277359 [patent_doc_number] => 20040236810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Parallel fast fourier transformation method of concealed-communication type' [patent_app_type] => new [patent_app_number] => 10/785110 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10009 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20040236810.pdf [firstpage_image] =>[orig_patent_app_number] => 10785110 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/785110
Parallel fast Fourier transformation method of concealed-communication type Feb 24, 2004 Issued
Array ( [id] => 7473842 [patent_doc_number] => 20040167955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Arithmetic device for multiple precision arithmetic for montgomery multiplication residue arithmetic' [patent_app_type] => new [patent_app_number] => 10/781634 [patent_app_country] => US [patent_app_date] => 2004-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6184 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20040167955.pdf [firstpage_image] =>[orig_patent_app_number] => 10781634 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/781634
Arithmetic device for multiple precision arithmetic for Montgomery multiplication residue arithmetic Feb 19, 2004 Issued
Array ( [id] => 7383852 [patent_doc_number] => 20040220990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Addition and multiplication in multisignal method, circuits for addition, subtraction, multiplication and division and their usage, and the four calculations by software tables' [patent_app_type] => new [patent_app_number] => 10/778541 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6800 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20040220990.pdf [firstpage_image] =>[orig_patent_app_number] => 10778541 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/778541
Addition and multiplication in multisignal method, circuits for addition, subtraction, multiplication and division and their usage, and the four calculations by software tables Feb 16, 2004 Abandoned
Array ( [id] => 135953 [patent_doc_number] => 07702704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Random number generating method and semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/588788 [patent_app_country] => US [patent_app_date] => 2004-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 36 [patent_no_of_words] => 17118 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/702/07702704.pdf [firstpage_image] =>[orig_patent_app_number] => 10588788 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/588788
Random number generating method and semiconductor integrated circuit device Feb 11, 2004 Issued
Array ( [id] => 7245866 [patent_doc_number] => 20040158594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Two-dimensional pyramid filter architecture' [patent_app_type] => new [patent_app_number] => 10/772630 [patent_app_country] => US [patent_app_date] => 2004-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5607 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20040158594.pdf [firstpage_image] =>[orig_patent_app_number] => 10772630 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/772630
Two-dimensional pyramid filter architecture Feb 3, 2004 Abandoned
Array ( [id] => 7456148 [patent_doc_number] => 20040186869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Transposition circuit' [patent_app_type] => new [patent_app_number] => 10/766484 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8871 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20040186869.pdf [firstpage_image] =>[orig_patent_app_number] => 10766484 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/766484
Transposition circuit Jan 28, 2004 Issued
Array ( [id] => 7099898 [patent_doc_number] => 20050131973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Numerical value conversion using a saturation limited arithmetic logic unit supporting variable resolution operands' [patent_app_type] => utility [patent_app_number] => 10/759988 [patent_app_country] => US [patent_app_date] => 2004-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20050131973.pdf [firstpage_image] =>[orig_patent_app_number] => 10759988 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/759988
Numerical value conversion using a saturation limited arithmetic logic unit supporting variable resolution operands Jan 14, 2004 Issued
Array ( [id] => 7432405 [patent_doc_number] => 20040230406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Probability generating apparatus' [patent_app_type] => new [patent_app_number] => 10/757369 [patent_app_country] => US [patent_app_date] => 2004-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 76 [patent_figures_cnt] => 76 [patent_no_of_words] => 24962 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20040230406.pdf [firstpage_image] =>[orig_patent_app_number] => 10757369 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/757369
Probability generating apparatus Jan 13, 2004 Issued
Array ( [id] => 146372 [patent_doc_number] => 07693928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Galois field linear transformer trellis system' [patent_app_type] => utility [patent_app_number] => 10/753301 [patent_app_country] => US [patent_app_date] => 2004-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 3407 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/693/07693928.pdf [firstpage_image] =>[orig_patent_app_number] => 10753301 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/753301
Galois field linear transformer trellis system Jan 6, 2004 Issued
Array ( [id] => 7261187 [patent_doc_number] => 20050144206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'System and method for precise calculation of alternative units of measure' [patent_app_type] => utility [patent_app_number] => 10/747981 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6058 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20050144206.pdf [firstpage_image] =>[orig_patent_app_number] => 10747981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/747981
System and method for precise calculation of alternative units of measure Dec 30, 2003 Issued
Array ( [id] => 137039 [patent_doc_number] => 07698358 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-13 [patent_title] => 'Programmable logic device with specialized functional block' [patent_app_type] => utility [patent_app_number] => 10/746448 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5520 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/698/07698358.pdf [firstpage_image] =>[orig_patent_app_number] => 10746448 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746448
Programmable logic device with specialized functional block Dec 23, 2003 Issued
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