Search

Chuong D. Ngo

Examiner (ID: 8858, Phone: (571)272-3731 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2787, 2306, 2121, 2899, 2124, 2182, 2183, 2193
Total Applications
2158
Issued Applications
1754
Pending Applications
68
Abandoned Applications
343

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 725607 [patent_doc_number] => 07051061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Dual use dual complex multiplier and complex divider' [patent_app_type] => utility [patent_app_number] => 10/744829 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2399 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 379 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/051/07051061.pdf [firstpage_image] =>[orig_patent_app_number] => 10744829 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/744829
Dual use dual complex multiplier and complex divider Dec 22, 2003 Issued
Array ( [id] => 6992262 [patent_doc_number] => 20050091299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Carry look-ahead adder having a reduced area' [patent_app_type] => utility [patent_app_number] => 10/740444 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5184 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20050091299.pdf [firstpage_image] =>[orig_patent_app_number] => 10740444 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/740444
Carry look-ahead adder having a reduced area Dec 21, 2003 Abandoned
Array ( [id] => 7154052 [patent_doc_number] => 20040172430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'Method and device for acquiring data' [patent_app_type] => new [patent_app_number] => 10/738975 [patent_app_country] => US [patent_app_date] => 2003-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5693 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20040172430.pdf [firstpage_image] =>[orig_patent_app_number] => 10738975 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/738975
Method and device for acquiring data Dec 18, 2003 Abandoned
Array ( [id] => 6994552 [patent_doc_number] => 20050134330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'DDS pulse generator architecture' [patent_app_type] => utility [patent_app_number] => 10/739591 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4131 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20050134330.pdf [firstpage_image] =>[orig_patent_app_number] => 10739591 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739591
DDS pulse generator architecture Dec 17, 2003 Issued
Array ( [id] => 417994 [patent_doc_number] => 07281025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-09 [patent_title] => 'Triggered DDS pulse generator architecture' [patent_app_type] => utility [patent_app_number] => 10/739761 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2448 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/281/07281025.pdf [firstpage_image] =>[orig_patent_app_number] => 10739761 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/739761
Triggered DDS pulse generator architecture Dec 17, 2003 Issued
Array ( [id] => 7084742 [patent_doc_number] => 20050050122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Object-oriented pseudo-random number generator interface' [patent_app_type] => utility [patent_app_number] => 10/741749 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9437 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20050050122.pdf [firstpage_image] =>[orig_patent_app_number] => 10741749 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/741749
Object-oriented pseudo-random number generator interface Dec 17, 2003 Abandoned
Array ( [id] => 7325673 [patent_doc_number] => 20040252829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Montgomery modular multiplier and method thereof using carry save addition' [patent_app_type] => new [patent_app_number] => 10/736832 [patent_app_country] => US [patent_app_date] => 2003-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4992 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20040252829.pdf [firstpage_image] =>[orig_patent_app_number] => 10736832 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/736832
Montgomery modular multiplier and method thereof using carry save addition Dec 16, 2003 Abandoned
Array ( [id] => 4641772 [patent_doc_number] => 08019805 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-09-13 [patent_title] => 'Apparatus and method for multiple pass extended precision floating point multiplication' [patent_app_type] => utility [patent_app_number] => 10/730800 [patent_app_country] => US [patent_app_date] => 2003-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8679 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/019/08019805.pdf [firstpage_image] =>[orig_patent_app_number] => 10730800 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/730800
Apparatus and method for multiple pass extended precision floating point multiplication Dec 8, 2003 Issued
Array ( [id] => 7476585 [patent_doc_number] => 20040122879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Digital multirate filtering' [patent_app_type] => new [patent_app_number] => 10/731618 [patent_app_country] => US [patent_app_date] => 2003-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3842 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20040122879.pdf [firstpage_image] =>[orig_patent_app_number] => 10731618 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/731618
Digital multirate filtering Dec 7, 2003 Issued
Array ( [id] => 7173477 [patent_doc_number] => 20040078415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Methods of factoring and modular arithmetic' [patent_app_type] => new [patent_app_number] => 10/726985 [patent_app_country] => US [patent_app_date] => 2003-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 14977 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078415.pdf [firstpage_image] =>[orig_patent_app_number] => 10726985 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/726985
Methods of factoring and modular arithmetic Dec 2, 2003 Issued
Array ( [id] => 7173398 [patent_doc_number] => 20040078406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Methods of factoring and modular arithmetic' [patent_app_type] => new [patent_app_number] => 10/726785 [patent_app_country] => US [patent_app_date] => 2003-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 14970 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078406.pdf [firstpage_image] =>[orig_patent_app_number] => 10726785 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/726785
Methods of factoring and modular arithmetic Dec 2, 2003 Issued
Array ( [id] => 6940865 [patent_doc_number] => 20050114428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Analog delay elements' [patent_app_type] => utility [patent_app_number] => 10/724443 [patent_app_country] => US [patent_app_date] => 2003-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3275 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20050114428.pdf [firstpage_image] =>[orig_patent_app_number] => 10724443 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/724443
Analog delay elements Nov 25, 2003 Issued
Array ( [id] => 6940853 [patent_doc_number] => 20050114416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Methods and apparatus for generating a delay using a counter' [patent_app_type] => utility [patent_app_number] => 10/723668 [patent_app_country] => US [patent_app_date] => 2003-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6427 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20050114416.pdf [firstpage_image] =>[orig_patent_app_number] => 10723668 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/723668
Methods and apparatus for generating a delay using a counter Nov 25, 2003 Issued
Array ( [id] => 279727 [patent_doc_number] => 07558812 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-07 [patent_title] => 'Structures for LUT-based arithmetic in PLDs' [patent_app_type] => utility [patent_app_number] => 10/723104 [patent_app_country] => US [patent_app_date] => 2003-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2697 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558812.pdf [firstpage_image] =>[orig_patent_app_number] => 10723104 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/723104
Structures for LUT-based arithmetic in PLDs Nov 25, 2003 Issued
Array ( [id] => 761469 [patent_doc_number] => 07020674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Device and method for performing multiple modulus conversion using inverse modulus multiplication' [patent_app_type] => utility [patent_app_number] => 10/722728 [patent_app_country] => US [patent_app_date] => 2003-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10889 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/020/07020674.pdf [firstpage_image] =>[orig_patent_app_number] => 10722728 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/722728
Device and method for performing multiple modulus conversion using inverse modulus multiplication Nov 24, 2003 Issued
Array ( [id] => 272148 [patent_doc_number] => 07565388 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-21 [patent_title] => 'Logic cell supporting addition of three binary words' [patent_app_type] => utility [patent_app_number] => 10/718968 [patent_app_country] => US [patent_app_date] => 2003-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5212 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/565/07565388.pdf [firstpage_image] =>[orig_patent_app_number] => 10718968 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/718968
Logic cell supporting addition of three binary words Nov 20, 2003 Issued
Array ( [id] => 6940854 [patent_doc_number] => 20050114417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Apparatus and method for filtering a signal' [patent_app_type] => utility [patent_app_number] => 10/719189 [patent_app_country] => US [patent_app_date] => 2003-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5937 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20050114417.pdf [firstpage_image] =>[orig_patent_app_number] => 10719189 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/719189
Apparatus and method for filtering a signal Nov 20, 2003 Issued
Array ( [id] => 6940859 [patent_doc_number] => 20050114422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'High performance implementation of exponent adjustment in a floating point design' [patent_app_type] => utility [patent_app_number] => 10/718303 [patent_app_country] => US [patent_app_date] => 2003-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4779 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20050114422.pdf [firstpage_image] =>[orig_patent_app_number] => 10718303 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/718303
High performance implementation of exponent adjustment in a floating point design Nov 19, 2003 Issued
Array ( [id] => 444057 [patent_doc_number] => 07260595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-21 [patent_title] => 'Logic circuit and method for carry and sum generation and method of designing such a logic circuit' [patent_app_type] => utility [patent_app_number] => 10/714408 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 19478 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/260/07260595.pdf [firstpage_image] =>[orig_patent_app_number] => 10714408 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/714408
Logic circuit and method for carry and sum generation and method of designing such a logic circuit Nov 13, 2003 Issued
Array ( [id] => 7293129 [patent_doc_number] => 20040111456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Filter circuit comprising an analog to digital converter' [patent_app_type] => new [patent_app_number] => 10/706053 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1361 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20040111456.pdf [firstpage_image] =>[orig_patent_app_number] => 10706053 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/706053
Filter circuit comprising an analog to digital converter Nov 12, 2003 Abandoned
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