
Chuong D. Ngo
Examiner (ID: 8858, Phone: (571)272-3731 , Office: P/2182 )
| Most Active Art Unit | 2193 |
| Art Unit(s) | 2787, 2306, 2121, 2899, 2124, 2182, 2183, 2193 |
| Total Applications | 2158 |
| Issued Applications | 1754 |
| Pending Applications | 68 |
| Abandoned Applications | 343 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7355463
[patent_doc_number] => 20040249474
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-09
[patent_title] => 'Compare-plus-tally instructions'
[patent_app_type] => new
[patent_app_number] => 10/403978
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4608
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0249/20040249474.pdf
[firstpage_image] =>[orig_patent_app_number] => 10403978
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/403978 | Compare-plus-tally instructions | Mar 30, 2003 | Abandoned |
Array
(
[id] => 6731711
[patent_doc_number] => 20030187901
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-02
[patent_title] => 'Method for performing integer divisions'
[patent_app_type] => new
[patent_app_number] => 10/400811
[patent_app_country] => US
[patent_app_date] => 2003-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2490
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0187/20030187901.pdf
[firstpage_image] =>[orig_patent_app_number] => 10400811
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/400811 | Method for performing integer divisions | Mar 26, 2003 | Issued |
Array
(
[id] => 7191411
[patent_doc_number] => 20040085095
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-06
[patent_title] => 'Device and method for adding and/or subtracting'
[patent_app_type] => new
[patent_app_number] => 10/401285
[patent_app_country] => US
[patent_app_date] => 2003-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3026
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 28
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0085/20040085095.pdf
[firstpage_image] =>[orig_patent_app_number] => 10401285
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/401285 | Device and method for adding and/or subtracting | Mar 26, 2003 | Abandoned |
Array
(
[id] => 431132
[patent_doc_number] => 07269616
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-11
[patent_title] => 'Transitive processing unit for performing complex operations'
[patent_app_type] => utility
[patent_app_number] => 10/394824
[patent_app_country] => US
[patent_app_date] => 2003-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 11502
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/269/07269616.pdf
[firstpage_image] =>[orig_patent_app_number] => 10394824
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/394824 | Transitive processing unit for performing complex operations | Mar 20, 2003 | Issued |
Array
(
[id] => 155842
[patent_doc_number] => 07685221
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-03-23
[patent_title] => 'Efficient remainder calculation for even divisors'
[patent_app_type] => utility
[patent_app_number] => 10/391129
[patent_app_country] => US
[patent_app_date] => 2003-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3201
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 256
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/685/07685221.pdf
[firstpage_image] =>[orig_patent_app_number] => 10391129
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/391129 | Efficient remainder calculation for even divisors | Mar 16, 2003 | Issued |
Array
(
[id] => 7672216
[patent_doc_number] => 20040181563
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-16
[patent_title] => 'Calculating device capable of performing arithmetical operations for discount'
[patent_app_type] => new
[patent_app_number] => 10/387557
[patent_app_country] => US
[patent_app_date] => 2003-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2533
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0181/20040181563.pdf
[firstpage_image] =>[orig_patent_app_number] => 10387557
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/387557 | Calculating device capable of performing arithmetical operations for discount | Mar 13, 2003 | Abandoned |
Array
(
[id] => 592429
[patent_doc_number] => 07461115
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-02
[patent_title] => 'Modular multiplier'
[patent_app_type] => utility
[patent_app_number] => 10/387009
[patent_app_country] => US
[patent_app_date] => 2003-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 46
[patent_no_of_words] => 17222
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/461/07461115.pdf
[firstpage_image] =>[orig_patent_app_number] => 10387009
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/387009 | Modular multiplier | Mar 10, 2003 | Issued |
Array
(
[id] => 7417086
[patent_doc_number] => 20040177104
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-09
[patent_title] => 'Multiply accumulator for two N bit multipliers and an M bit addend'
[patent_app_type] => new
[patent_app_number] => 10/384428
[patent_app_country] => US
[patent_app_date] => 2003-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2718
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 249
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0177/20040177104.pdf
[firstpage_image] =>[orig_patent_app_number] => 10384428
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/384428 | Multiply accumulator for two N bit multipliers and an M bit addend | Mar 6, 2003 | Issued |
Array
(
[id] => 7672211
[patent_doc_number] => 20040181568
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-16
[patent_title] => 'Method for recognition of full-word saturating addition and subtraction'
[patent_app_type] => new
[patent_app_number] => 10/382578
[patent_app_country] => US
[patent_app_date] => 2003-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7312
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0181/20040181568.pdf
[firstpage_image] =>[orig_patent_app_number] => 10382578
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/382578 | Method for recognition of full-word saturating addition and subtraction | Mar 6, 2003 | Issued |
Array
(
[id] => 599705
[patent_doc_number] => 07440987
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-10-21
[patent_title] => '16 bit quadrature direct digital frequency synthesizer using interpolative angle rotation'
[patent_app_type] => utility
[patent_app_number] => 10/373469
[patent_app_country] => US
[patent_app_date] => 2003-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 6720
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/440/07440987.pdf
[firstpage_image] =>[orig_patent_app_number] => 10373469
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/373469 | 16 bit quadrature direct digital frequency synthesizer using interpolative angle rotation | Feb 24, 2003 | Issued |
Array
(
[id] => 604579
[patent_doc_number] => 07433908
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-07
[patent_title] => 'Selective-partial-update proportionate normalized least-mean-square adaptive filtering for network echo cancellation'
[patent_app_type] => utility
[patent_app_number] => 10/374738
[patent_app_country] => US
[patent_app_date] => 2003-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 5761
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/433/07433908.pdf
[firstpage_image] =>[orig_patent_app_number] => 10374738
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/374738 | Selective-partial-update proportionate normalized least-mean-square adaptive filtering for network echo cancellation | Feb 24, 2003 | Issued |
Array
(
[id] => 653435
[patent_doc_number] => 07113968
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-09-26
[patent_title] => 'Method and apparatus for efficiently performing Galois field multiplication'
[patent_app_type] => utility
[patent_app_number] => 10/371298
[patent_app_country] => US
[patent_app_date] => 2003-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 12042
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/113/07113968.pdf
[firstpage_image] =>[orig_patent_app_number] => 10371298
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/371298 | Method and apparatus for efficiently performing Galois field multiplication | Feb 20, 2003 | Issued |
Array
(
[id] => 666621
[patent_doc_number] => 07103624
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-05
[patent_title] => 'Comparator circuit and method'
[patent_app_type] => utility
[patent_app_number] => 10/368397
[patent_app_country] => US
[patent_app_date] => 2003-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4490
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/103/07103624.pdf
[firstpage_image] =>[orig_patent_app_number] => 10368397
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/368397 | Comparator circuit and method | Feb 19, 2003 | Issued |
Array
(
[id] => 1011228
[patent_doc_number] => 06901419
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-31
[patent_title] => 'Arithmetic unit'
[patent_app_type] => utility
[patent_app_number] => 10/366355
[patent_app_country] => US
[patent_app_date] => 2003-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 20
[patent_no_of_words] => 11191
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/901/06901419.pdf
[firstpage_image] =>[orig_patent_app_number] => 10366355
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/366355 | Arithmetic unit | Feb 13, 2003 | Issued |
Array
(
[id] => 561056
[patent_doc_number] => 07165084
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-16
[patent_title] => 'Microprocessor with selectivity available random number generator based on self-test result'
[patent_app_type] => utility
[patent_app_number] => 10/365599
[patent_app_country] => US
[patent_app_date] => 2003-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 26
[patent_no_of_words] => 20798
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/165/07165084.pdf
[firstpage_image] =>[orig_patent_app_number] => 10365599
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/365599 | Microprocessor with selectivity available random number generator based on self-test result | Feb 10, 2003 | Issued |
Array
(
[id] => 507582
[patent_doc_number] => 07209939
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-24
[patent_title] => 'Precision improvement method for the Strassen/Winograd matrix multiplication method'
[patent_app_type] => utility
[patent_app_number] => 10/364617
[patent_app_country] => US
[patent_app_date] => 2003-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3406
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/209/07209939.pdf
[firstpage_image] =>[orig_patent_app_number] => 10364617
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/364617 | Precision improvement method for the Strassen/Winograd matrix multiplication method | Feb 9, 2003 | Issued |
Array
(
[id] => 610700
[patent_doc_number] => 07152088
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-19
[patent_title] => 'SQRT calculator capable of reducing error'
[patent_app_type] => utility
[patent_app_number] => 10/359539
[patent_app_country] => US
[patent_app_date] => 2003-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 4971
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 314
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/152/07152088.pdf
[firstpage_image] =>[orig_patent_app_number] => 10359539
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/359539 | SQRT calculator capable of reducing error | Feb 6, 2003 | Issued |
Array
(
[id] => 752614
[patent_doc_number] => 07028068
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-04-11
[patent_title] => 'Alternate phase dual compression-tree multiplier'
[patent_app_type] => utility
[patent_app_number] => 10/357978
[patent_app_country] => US
[patent_app_date] => 2003-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7929
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/028/07028068.pdf
[firstpage_image] =>[orig_patent_app_number] => 10357978
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/357978 | Alternate phase dual compression-tree multiplier | Feb 3, 2003 | Issued |
Array
(
[id] => 7391132
[patent_doc_number] => 20040083253
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-29
[patent_title] => 'Method and apparatus for efficient matrix multiplication in a direct sequence CDMA system'
[patent_app_type] => new
[patent_app_number] => 10/357124
[patent_app_country] => US
[patent_app_date] => 2003-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3432
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0083/20040083253.pdf
[firstpage_image] =>[orig_patent_app_number] => 10357124
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/357124 | Method and apparatus for efficient matrix multiplication in a direct sequence CDMA system | Feb 2, 2003 | Issued |
Array
(
[id] => 626158
[patent_doc_number] => 07139787
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-11-21
[patent_title] => 'Multiply execution unit for performing integer and XOR multiplication'
[patent_app_type] => utility
[patent_app_number] => 10/354354
[patent_app_country] => US
[patent_app_date] => 2003-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4455
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/139/07139787.pdf
[firstpage_image] =>[orig_patent_app_number] => 10354354
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/354354 | Multiply execution unit for performing integer and XOR multiplication | Jan 29, 2003 | Issued |