Chuong D. Ngo

Array ( [id] => 6831286 [patent_doc_number] => 20030182344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Integrated multiplier circuit with interchanged interconnections' [patent_app_type] => new [patent_app_number] => 10/354125 [patent_app_country] => US [patent_app_date] => 2003-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6235 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20030182344.pdf [firstpage_image] =>[orig_patent_app_number] => 10354125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6850537 [patent_doc_number] => 20030142739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'Digital filter for filtering time-division-multiplexed signal' [patent_app_type] => new [patent_app_number] => 10/353977 [patent_app_country] => US [patent_app_date] => 2003-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3760 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20030142739.pdf [firstpage_image] =>[orig_patent_app_number] => 10353977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7290458 [patent_doc_number] => 20040148324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Block-partitioned technique for solving a system of linear equations represented by a matrix with static and dynamic entries' [patent_app_type] => new [patent_app_number] => 10/354330 [patent_app_country] => US [patent_app_date] => 2003-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8336 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20040148324.pdf [firstpage_image] =>[orig_patent_app_number] => 10354330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 244934 [patent_doc_number] => 07590677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Processor with summation instruction using overflow counter' [patent_app_type] => utility [patent_app_number] => 10/349224 [patent_app_country] => US [patent_app_date] => 2003-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4213 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590677.pdf [firstpage_image] =>[orig_patent_app_number] => 10349224 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7312200 [patent_doc_number] => 20040143619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Sparce-redundant fixed point arithmetic modules' [patent_app_type] => new [patent_app_number] => 10/348538 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3307 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20040143619.pdf [firstpage_image] =>[orig_patent_app_number] => 10348538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 671370 [patent_doc_number] => 07096243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-22 [patent_title] => 'Flexible decimator' [patent_app_type] => utility [patent_app_number] => 10/348308 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4477 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/096/07096243.pdf [firstpage_image] =>[orig_patent_app_number] => 10348308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7312189 [patent_doc_number] => 20040143614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Hiding the internal state of a random number generator' [patent_app_type] => new [patent_app_number] => 10/347755 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3624 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20040143614.pdf [firstpage_image] =>[orig_patent_app_number] => 10347755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 623007 [patent_doc_number] => 07143127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Scaling method by using symmetrical middle-point slope control (SMSC)' [patent_app_type] => utility [patent_app_number] => 10/342790 [patent_app_country] => US [patent_app_date] => 2003-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3688 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143127.pdf [firstpage_image] =>[orig_patent_app_number] => 10342790 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6660885 [patent_doc_number] => 20030135529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Apparatus and method for compact Haar transform' [patent_app_type] => new [patent_app_number] => 10/340656 [patent_app_country] => US [patent_app_date] => 2003-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9477 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20030135529.pdf [firstpage_image] =>[orig_patent_app_number] => 10340656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 839647 [patent_doc_number] => 07395294 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-01 [patent_title] => 'Arithmetic logic unit' [patent_app_type] => utility [patent_app_number] => 10/340917 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 5933 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/395/07395294.pdf [firstpage_image] =>[orig_patent_app_number] => 10340917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 525650 [patent_doc_number] => 07200631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'Method and apparatus for determining an inverse square root of a given positive-definite hermitian matrix' [patent_app_type] => utility [patent_app_number] => 10/340575 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2106 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/200/07200631.pdf [firstpage_image] =>[orig_patent_app_number] => 10340575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6684827 [patent_doc_number] => 20030120691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Hadamard transformation method and apparatus' [patent_app_type] => new [patent_app_number] => 10/322598 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5796 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20030120691.pdf [firstpage_image] =>[orig_patent_app_number] => 10322598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 629635 [patent_doc_number] => 07136890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Inverse discrete cosine transform apparatus' [patent_app_type] => utility [patent_app_number] => 10/321369 [patent_app_country] => US [patent_app_date] => 2002-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6301 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/136/07136890.pdf [firstpage_image] =>[orig_patent_app_number] => 10321369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6702929 [patent_doc_number] => 20030225809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'DUAL USE DUAL COMPLEX MULTIPLIER AND COMPLEX DIVIDER' [patent_app_type] => new [patent_app_number] => 10/322160 [patent_app_country] => US [patent_app_date] => 2002-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2137 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20030225809.pdf [firstpage_image] =>[orig_patent_app_number] => 10322160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7476711 [patent_doc_number] => 20040098438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Method of generating a multiply accumulator with an optimum timing and generator thereof' [patent_app_type] => new [patent_app_number] => 10/320458 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2421 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20040098438.pdf [firstpage_image] =>[orig_patent_app_number] => 10320458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6786799 [patent_doc_number] => 20030138038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Echo and near end cross talk reduction' [patent_app_type] => new [patent_app_number] => 10/320767 [patent_app_country] => US [patent_app_date] => 2002-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 16605 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20030138038.pdf [firstpage_image] =>[orig_patent_app_number] => 10320767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 472652 [patent_doc_number] => 07233966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-19 [patent_title] => 'Method and device for generating an output signal as a mathematical function of an input signal' [patent_app_type] => utility [patent_app_number] => 10/321829 [patent_app_country] => US [patent_app_date] => 2002-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4102 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/233/07233966.pdf [firstpage_image] =>[orig_patent_app_number] => 10321829 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 700878 [patent_doc_number] => 07072922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Integrated circuit and process for identifying minimum or maximum input value among plural inputs' [patent_app_type] => utility [patent_app_number] => 10/319219 [patent_app_country] => US [patent_app_date] => 2002-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3693 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/072/07072922.pdf [firstpage_image] =>[orig_patent_app_number] => 10319219 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6731707 [patent_doc_number] => 20030187897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Numeric processor, a numeric processing method, and a data processing apparatus or computer program incorporating a numeric processing mechanism' [patent_app_type] => new [patent_app_number] => 10/319270 [patent_app_country] => US [patent_app_date] => 2002-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5073 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20030187897.pdf [firstpage_image] =>[orig_patent_app_number] => 10319270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7308556 [patent_doc_number] => 20040117423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Signed integer long division apparatus and methods for use with processors' [patent_app_type] => new [patent_app_number] => 10/316708 [patent_app_country] => US [patent_app_date] => 2002-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3394 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20040117423.pdf [firstpage_image] =>[orig_patent_app_number] => 10316708 [rel_patent_id] =>[rel_patent_doc_number] =>)