
Chuong D. Ngo
Examiner (ID: 8858, Phone: (571)272-3731 , Office: P/2182 )
| Most Active Art Unit | 2193 |
| Art Unit(s) | 2787, 2306, 2121, 2899, 2124, 2182, 2183, 2193 |
| Total Applications | 2158 |
| Issued Applications | 1754 |
| Pending Applications | 68 |
| Abandoned Applications | 343 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1105947
[patent_doc_number] => 06816877
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-09
[patent_title] => 'Apparatus for digital multiplication using redundant binary arithmetic'
[patent_app_type] => B2
[patent_app_number] => 09/832869
[patent_app_country] => US
[patent_app_date] => 2001-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 9762
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/816/06816877.pdf
[firstpage_image] =>[orig_patent_app_number] => 09832869
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/832869 | Apparatus for digital multiplication using redundant binary arithmetic | Apr 11, 2001 | Issued |
Array
(
[id] => 6114793
[patent_doc_number] => 20020174158
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-21
[patent_title] => 'Adder circuit with a regular structure'
[patent_app_type] => new
[patent_app_number] => 09/827569
[patent_app_country] => US
[patent_app_date] => 2001-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4439
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0174/20020174158.pdf
[firstpage_image] =>[orig_patent_app_number] => 09827569
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/827569 | Adder circuit with a regular structure | Apr 4, 2001 | Issued |
Array
(
[id] => 805940
[patent_doc_number] => 07424506
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-09
[patent_title] => 'Architecture and related methods for efficiently performing complex arithmetic'
[patent_app_type] => utility
[patent_app_number] => 09/823928
[patent_app_country] => US
[patent_app_date] => 2001-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5454
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/424/07424506.pdf
[firstpage_image] =>[orig_patent_app_number] => 09823928
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/823928 | Architecture and related methods for efficiently performing complex arithmetic | Mar 30, 2001 | Issued |
Array
(
[id] => 6114788
[patent_doc_number] => 20020174156
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-21
[patent_title] => 'Round-off algorithm without bias for 2\'s complemetnt data'
[patent_app_type] => new
[patent_app_number] => 09/821178
[patent_app_country] => US
[patent_app_date] => 2001-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2597
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0174/20020174156.pdf
[firstpage_image] =>[orig_patent_app_number] => 09821178
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/821178 | Round-off algorithm without bias for 2's complement data | Mar 28, 2001 | Issued |
Array
(
[id] => 6114768
[patent_doc_number] => 20020174151
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-21
[patent_title] => 'Calculation method and apparatus'
[patent_app_type] => new
[patent_app_number] => 09/819778
[patent_app_country] => US
[patent_app_date] => 2001-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4546
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0174/20020174151.pdf
[firstpage_image] =>[orig_patent_app_number] => 09819778
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/819778 | Calculation method and apparatus | Mar 27, 2001 | Issued |
Array
(
[id] => 1168512
[patent_doc_number] => 06766286
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-20
[patent_title] => 'Pyramid filter'
[patent_app_type] => B2
[patent_app_number] => 09/820108
[patent_app_country] => US
[patent_app_date] => 2001-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 2492
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 17
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/766/06766286.pdf
[firstpage_image] =>[orig_patent_app_number] => 09820108
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/820108 | Pyramid filter | Mar 27, 2001 | Issued |
Array
(
[id] => 6550957
[patent_doc_number] => 20020194232
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-19
[patent_title] => 'Minimum and maximum operations to facilitate interval multiplication and/or interval division'
[patent_app_type] => new
[patent_app_number] => 09/818021
[patent_app_country] => US
[patent_app_date] => 2001-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5289
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0194/20020194232.pdf
[firstpage_image] =>[orig_patent_app_number] => 09818021
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/818021 | Minimum and maximum operations to facilitate interval multiplication and/or interval division | Mar 25, 2001 | Issued |
Array
(
[id] => 6908577
[patent_doc_number] => 20010011344
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-02
[patent_title] => 'Data processing system and register file'
[patent_app_type] => new
[patent_app_number] => 09/811700
[patent_app_country] => US
[patent_app_date] => 2001-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6691
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0011/20010011344.pdf
[firstpage_image] =>[orig_patent_app_number] => 09811700
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/811700 | Data processing system and register file | Mar 19, 2001 | Issued |
Array
(
[id] => 6775338
[patent_doc_number] => 20030018676
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-23
[patent_title] => 'Multi-function floating point arithmetic pipeline'
[patent_app_type] => new
[patent_app_number] => 09/808138
[patent_app_country] => US
[patent_app_date] => 2001-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 11090
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20030018676.pdf
[firstpage_image] =>[orig_patent_app_number] => 09808138
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/808138 | Multi-function floating point arithmetic pipeline | Mar 14, 2001 | Issued |
Array
(
[id] => 7416434
[patent_doc_number] => 20040207725
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-21
[patent_title] => 'Video compression/decompression processing and processors'
[patent_app_type] => new
[patent_app_number] => 10/470571
[patent_app_country] => US
[patent_app_date] => 2001-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 14767
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0207/20040207725.pdf
[firstpage_image] =>[orig_patent_app_number] => 10470571
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/470571 | Apparatus for multiplying and accumulating numeric quantities | Feb 28, 2001 | Issued |
Array
(
[id] => 6908523
[patent_doc_number] => 20010011290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-02
[patent_title] => 'Interpolating filter banks in arbitrary dimensions'
[patent_app_type] => new
[patent_app_number] => 09/794865
[patent_app_country] => US
[patent_app_date] => 2001-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 11793
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0011/20010011290.pdf
[firstpage_image] =>[orig_patent_app_number] => 09794865
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/794865 | Interpolating filter banks in arbitrary dimensions | Feb 26, 2001 | Issued |
Array
(
[id] => 957966
[patent_doc_number] => 06957238
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-10-18
[patent_title] => 'Method and system for deterministic pseudo-random valid entry resolution'
[patent_app_type] => utility
[patent_app_number] => 09/792599
[patent_app_country] => US
[patent_app_date] => 2001-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2556
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/957/06957238.pdf
[firstpage_image] =>[orig_patent_app_number] => 09792599
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/792599 | Method and system for deterministic pseudo-random valid entry resolution | Feb 22, 2001 | Issued |
Array
(
[id] => 989352
[patent_doc_number] => 06922715
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-26
[patent_title] => 'Computer implemented method and program for estimation of characteristic values of matrixes using statistical sampling'
[patent_app_type] => utility
[patent_app_number] => 09/791198
[patent_app_country] => US
[patent_app_date] => 2001-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 6630
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/922/06922715.pdf
[firstpage_image] =>[orig_patent_app_number] => 09791198
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/791198 | Computer implemented method and program for estimation of characteristic values of matrixes using statistical sampling | Feb 22, 2001 | Issued |
Array
(
[id] => 6889838
[patent_doc_number] => 20010025293
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-09-27
[patent_title] => 'Divider'
[patent_app_type] => new
[patent_app_number] => 09/778258
[patent_app_country] => US
[patent_app_date] => 2001-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5075
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0025/20010025293.pdf
[firstpage_image] =>[orig_patent_app_number] => 09778258
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/778258 | Divider | Feb 6, 2001 | Issued |
Array
(
[id] => 6161080
[patent_doc_number] => 20020147753
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-10
[patent_title] => 'Methods and systems for raising a numerical value to a fractional power'
[patent_app_type] => new
[patent_app_number] => 09/773058
[patent_app_country] => US
[patent_app_date] => 2001-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6138
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0147/20020147753.pdf
[firstpage_image] =>[orig_patent_app_number] => 09773058
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/773058 | Methods and systems for raising a numerical value to a fractional power | Jan 29, 2001 | Abandoned |
Array
(
[id] => 6888018
[patent_doc_number] => 20010009012
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-07-19
[patent_title] => 'High speed multiplication apparatus of Wallace tree type with high area efficiency'
[patent_app_type] => new-utility
[patent_app_number] => 09/756269
[patent_app_country] => US
[patent_app_date] => 2001-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10697
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0009/20010009012.pdf
[firstpage_image] =>[orig_patent_app_number] => 09756269
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/756269 | High speed multiplication apparatus of Wallace tree type with high area efficiency | Jan 8, 2001 | Abandoned |
Array
(
[id] => 6896750
[patent_doc_number] => 20010027540
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-10-04
[patent_title] => 'Apparatus and method for detecting operation value using lookup-table'
[patent_app_type] => new
[patent_app_number] => 09/755189
[patent_app_country] => US
[patent_app_date] => 2001-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3109
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0027/20010027540.pdf
[firstpage_image] =>[orig_patent_app_number] => 09755189
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/755189 | Apparatus and method for detecting operation value using lookup-table | Jan 7, 2001 | Issued |
Array
(
[id] => 1184331
[patent_doc_number] => 06748405
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-08
[patent_title] => 'Method and circuits for performing the quick search of the minimum/maximum value among a set of numbers'
[patent_app_type] => B2
[patent_app_number] => 09/754639
[patent_app_country] => US
[patent_app_date] => 2001-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 6693
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 309
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/748/06748405.pdf
[firstpage_image] =>[orig_patent_app_number] => 09754639
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/754639 | Method and circuits for performing the quick search of the minimum/maximum value among a set of numbers | Jan 3, 2001 | Issued |
Array
(
[id] => 6449340
[patent_doc_number] => 20020129074
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-09-12
[patent_title] => 'Modulo remainder generator'
[patent_app_type] => new
[patent_app_number] => 09/754479
[patent_app_country] => US
[patent_app_date] => 2001-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3101
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0129/20020129074.pdf
[firstpage_image] =>[orig_patent_app_number] => 09754479
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/754479 | Modulo remainder generator | Jan 3, 2001 | Issued |
Array
(
[id] => 1200758
[patent_doc_number] => 06728744
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-27
[patent_title] => 'Wide word multiplier using booth encoding'
[patent_app_type] => B2
[patent_app_number] => 09/751399
[patent_app_country] => US
[patent_app_date] => 2001-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 8336
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/728/06728744.pdf
[firstpage_image] =>[orig_patent_app_number] => 09751399
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/751399 | Wide word multiplier using booth encoding | Jan 1, 2001 | Issued |