Search

Chuong D. Ngo

Examiner (ID: 8858, Phone: (571)272-3731 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2787, 2306, 2121, 2899, 2124, 2182, 2183, 2193
Total Applications
2158
Issued Applications
1754
Pending Applications
68
Abandoned Applications
343

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1552494 [patent_doc_number] => 06446101 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Apparatus for fast determination of a prescribable number of highest value signals' [patent_app_type] => B1 [patent_app_number] => 09/388820 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1834 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446101.pdf [firstpage_image] =>[orig_patent_app_number] => 09388820 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/388820
Apparatus for fast determination of a prescribable number of highest value signals Aug 31, 1999 Issued
Array ( [id] => 1294576 [patent_doc_number] => 06640236 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Method and apparatus for generating multiple bits of a pseudonoise sequence with each clock pulse by computing the bits in parallel' [patent_app_type] => B1 [patent_app_number] => 09/386600 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5030 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/640/06640236.pdf [firstpage_image] =>[orig_patent_app_number] => 09386600 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/386600
Method and apparatus for generating multiple bits of a pseudonoise sequence with each clock pulse by computing the bits in parallel Aug 30, 1999 Issued
Array ( [id] => 1505772 [patent_doc_number] => 06487575 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Early completion of iterative division' [patent_app_type] => B1 [patent_app_number] => 09/385188 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 15728 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487575.pdf [firstpage_image] =>[orig_patent_app_number] => 09385188 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/385188
Early completion of iterative division Aug 29, 1999 Issued
Array ( [id] => 7613918 [patent_doc_number] => 06898613 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-24 [patent_title] => 'Arithmetic circuits for use with the residue number system' [patent_app_type] => utility [patent_app_number] => 09/383478 [patent_app_country] => US [patent_app_date] => 1999-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5515 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898613.pdf [firstpage_image] =>[orig_patent_app_number] => 09383478 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/383478
Arithmetic circuits for use with the residue number system Aug 25, 1999 Issued
Array ( [id] => 1456484 [patent_doc_number] => 06457036 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'System for accurately performing an integer multiply-divide operation' [patent_app_type] => B1 [patent_app_number] => 09/379678 [patent_app_country] => US [patent_app_date] => 1999-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457036.pdf [firstpage_image] =>[orig_patent_app_number] => 09379678 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/379678
System for accurately performing an integer multiply-divide operation Aug 23, 1999 Issued
Array ( [id] => 7638686 [patent_doc_number] => 06397234 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'System and apparatus for the detection of randomness in time series distributions made up of sparse data sets' [patent_app_type] => B1 [patent_app_number] => 09/379210 [patent_app_country] => US [patent_app_date] => 1999-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4384 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397234.pdf [firstpage_image] =>[orig_patent_app_number] => 09379210 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/379210
System and apparatus for the detection of randomness in time series distributions made up of sparse data sets Aug 19, 1999 Issued
Array ( [id] => 1524713 [patent_doc_number] => 06415308 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Converting negative floating point numbers to integer notation without two\'s complement hardware' [patent_app_type] => B1 [patent_app_number] => 09/377099 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7101 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415308.pdf [firstpage_image] =>[orig_patent_app_number] => 09377099 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/377099
Converting negative floating point numbers to integer notation without two's complement hardware Aug 18, 1999 Issued
Array ( [id] => 1119769 [patent_doc_number] => 06801924 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-05 [patent_title] => 'Formatting denormal numbers for processing in a pipelined floating point unit' [patent_app_type] => B1 [patent_app_number] => 09/377140 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6563 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/801/06801924.pdf [firstpage_image] =>[orig_patent_app_number] => 09377140 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/377140
Formatting denormal numbers for processing in a pipelined floating point unit Aug 18, 1999 Issued
Array ( [id] => 1519425 [patent_doc_number] => 06421696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'System and method for high speed execution of Fast Fourier Transforms utilizing SIMD instructions on a general purpose processor' [patent_app_type] => B1 [patent_app_number] => 09/375458 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16218 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421696.pdf [firstpage_image] =>[orig_patent_app_number] => 09375458 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/375458
System and method for high speed execution of Fast Fourier Transforms utilizing SIMD instructions on a general purpose processor Aug 16, 1999 Issued
Array ( [id] => 1532868 [patent_doc_number] => 06480870 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Random number generator using lehmer algorithm' [patent_app_type] => B1 [patent_app_number] => 09/369398 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6832 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480870.pdf [firstpage_image] =>[orig_patent_app_number] => 09369398 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/369398
Random number generator using lehmer algorithm Aug 5, 1999 Issued
Array ( [id] => 945616 [patent_doc_number] => 06968352 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-22 [patent_title] => 'Device for digital processing with frequency filtering and reduced computation complexity' [patent_app_type] => utility [patent_app_number] => 09/762388 [patent_app_country] => US [patent_app_date] => 1999-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 26 [patent_no_of_words] => 10515 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/968/06968352.pdf [firstpage_image] =>[orig_patent_app_number] => 09762388 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/762388
Device for digital processing with frequency filtering and reduced computation complexity Aug 4, 1999 Issued
Array ( [id] => 1595664 [patent_doc_number] => 06484193 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Fully pipelined parallel multiplier with a fast clock cycle' [patent_app_type] => B1 [patent_app_number] => 09/365160 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 1 [patent_no_of_words] => 4738 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484193.pdf [firstpage_image] =>[orig_patent_app_number] => 09365160 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/365160
Fully pipelined parallel multiplier with a fast clock cycle Jul 29, 1999 Issued
Array ( [id] => 1297756 [patent_doc_number] => 06631392 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Method and apparatus for predicting floating-point exceptions' [patent_app_type] => B1 [patent_app_number] => 09/363638 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6708 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631392.pdf [firstpage_image] =>[orig_patent_app_number] => 09363638 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363638
Method and apparatus for predicting floating-point exceptions Jul 29, 1999 Issued
Array ( [id] => 1462288 [patent_doc_number] => 06427157 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Fir filter structure with time- varying coefficients and filtering method for digital data scaling' [patent_app_type] => B1 [patent_app_number] => 09/363799 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5797 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427157.pdf [firstpage_image] =>[orig_patent_app_number] => 09363799 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363799
Fir filter structure with time- varying coefficients and filtering method for digital data scaling Jul 28, 1999 Issued
Array ( [id] => 1566901 [patent_doc_number] => 06438570 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'FPGA implemented bit-serial multiplier and infinite impulse response' [patent_app_type] => B1 [patent_app_number] => 09/358508 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 7041 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438570.pdf [firstpage_image] =>[orig_patent_app_number] => 09358508 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/358508
FPGA implemented bit-serial multiplier and infinite impulse response Jul 20, 1999 Issued
Array ( [id] => 1443891 [patent_doc_number] => 06496846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Conditional carry encoding for carry select adder' [patent_app_type] => B1 [patent_app_number] => 09/352259 [patent_app_country] => US [patent_app_date] => 1999-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5459 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496846.pdf [firstpage_image] =>[orig_patent_app_number] => 09352259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/352259
Conditional carry encoding for carry select adder Jul 12, 1999 Issued
Array ( [id] => 1595656 [patent_doc_number] => 06484191 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Apparatus and method for the real-time calculation of local variance in images' [patent_app_type] => B1 [patent_app_number] => 09/346599 [patent_app_country] => US [patent_app_date] => 1999-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8397 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 651 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484191.pdf [firstpage_image] =>[orig_patent_app_number] => 09346599 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/346599
Apparatus and method for the real-time calculation of local variance in images Jul 1, 1999 Issued
Array ( [id] => 1465849 [patent_doc_number] => 06393446 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => '32-bit and 64-bit dual mode rotator' [patent_app_type] => B1 [patent_app_number] => 09/343450 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5518 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393446.pdf [firstpage_image] =>[orig_patent_app_number] => 09343450 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343450
32-bit and 64-bit dual mode rotator Jun 29, 1999 Issued
Array ( [id] => 1415675 [patent_doc_number] => 06532441 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Parallel oversampled decimator filter' [patent_app_type] => B1 [patent_app_number] => 09/334038 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2339 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532441.pdf [firstpage_image] =>[orig_patent_app_number] => 09334038 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/334038
Parallel oversampled decimator filter Jun 14, 1999 Issued
Array ( [id] => 1465852 [patent_doc_number] => 06393448 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Optical random-number generator based on single-photon statistics at the optical beam splitter' [patent_app_type] => B1 [patent_app_number] => 09/284178 [patent_app_country] => US [patent_app_date] => 1999-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2639 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393448.pdf [firstpage_image] =>[orig_patent_app_number] => 09284178 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/284178
Optical random-number generator based on single-photon statistics at the optical beam splitter Jun 13, 1999 Issued
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