Search

Chuong D. Ngo

Examiner (ID: 8858, Phone: (571)272-3731 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2787, 2306, 2121, 2899, 2124, 2182, 2183, 2193
Total Applications
2158
Issued Applications
1754
Pending Applications
68
Abandoned Applications
343

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4297733 [patent_doc_number] => 06282555 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Orthogonal transform processor' [patent_app_type] => 1 [patent_app_number] => 9/237856 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5958 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282555.pdf [firstpage_image] =>[orig_patent_app_number] => 237856 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/237856
Orthogonal transform processor Jan 26, 1999 Issued
Array ( [id] => 1474676 [patent_doc_number] => 06408320 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Instruction set architecture with versatile adder carry control' [patent_app_type] => B1 [patent_app_number] => 09/238236 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4902 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408320.pdf [firstpage_image] =>[orig_patent_app_number] => 09238236 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238236
Instruction set architecture with versatile adder carry control Jan 26, 1999 Issued
Array ( [id] => 1501321 [patent_doc_number] => 06405229 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Digital filters' [patent_app_type] => B1 [patent_app_number] => 09/237520 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11341 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405229.pdf [firstpage_image] =>[orig_patent_app_number] => 09237520 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/237520
Digital filters Jan 25, 1999 Issued
Array ( [id] => 1567150 [patent_doc_number] => 06363406 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Audio data compression/expansion apparatus and digital filter' [patent_app_type] => B1 [patent_app_number] => 09/237719 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8617 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363406.pdf [firstpage_image] =>[orig_patent_app_number] => 09237719 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/237719
Audio data compression/expansion apparatus and digital filter Jan 25, 1999 Issued
Array ( [id] => 1532876 [patent_doc_number] => 06480872 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Floating-point and integer multiply-add and multiply-accumulate' [patent_app_type] => B1 [patent_app_number] => 09/235148 [patent_app_country] => US [patent_app_date] => 1999-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480872.pdf [firstpage_image] =>[orig_patent_app_number] => 09235148 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/235148
Floating-point and integer multiply-add and multiply-accumulate Jan 20, 1999 Issued
Array ( [id] => 4373229 [patent_doc_number] => 06292819 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Binary and decimal adder unit' [patent_app_type] => 1 [patent_app_number] => 9/235028 [patent_app_country] => US [patent_app_date] => 1999-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5546 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292819.pdf [firstpage_image] =>[orig_patent_app_number] => 235028 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/235028
Binary and decimal adder unit Jan 20, 1999 Issued
Array ( [id] => 4403227 [patent_doc_number] => 06263354 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Reduced multiplier digital IIR filters' [patent_app_type] => 1 [patent_app_number] => 9/232430 [patent_app_country] => US [patent_app_date] => 1999-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 7303 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263354.pdf [firstpage_image] =>[orig_patent_app_number] => 232430 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/232430
Reduced multiplier digital IIR filters Jan 14, 1999 Issued
Array ( [id] => 4398655 [patent_doc_number] => 06295546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method and apparatus for eliminating the transpose buffer during a decomposed forward or inverse 2-dimensional discrete cosine transform through operand decomposition, storage and retrieval' [patent_app_type] => 1 [patent_app_number] => 9/223494 [patent_app_country] => US [patent_app_date] => 1998-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 81 [patent_figures_cnt] => 88 [patent_no_of_words] => 43740 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295546.pdf [firstpage_image] =>[orig_patent_app_number] => 223494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/223494
Method and apparatus for eliminating the transpose buffer during a decomposed forward or inverse 2-dimensional discrete cosine transform through operand decomposition, storage and retrieval Dec 30, 1998 Issued
Array ( [id] => 4401351 [patent_doc_number] => 06279019 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Decimation filtering apparatus and method' [patent_app_type] => 1 [patent_app_number] => 9/224811 [patent_app_country] => US [patent_app_date] => 1998-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 8922 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279019.pdf [firstpage_image] =>[orig_patent_app_number] => 224811 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224811
Decimation filtering apparatus and method Dec 30, 1998 Issued
Array ( [id] => 1501314 [patent_doc_number] => 06405227 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Digital crossover and parametric equalizer' [patent_app_type] => B1 [patent_app_number] => 09/224008 [patent_app_country] => US [patent_app_date] => 1998-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5753 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405227.pdf [firstpage_image] =>[orig_patent_app_number] => 09224008 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224008
Digital crossover and parametric equalizer Dec 30, 1998 Issued
Array ( [id] => 4279794 [patent_doc_number] => 06260052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Digital signal processing apparatus and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/222822 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3421 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260052.pdf [firstpage_image] =>[orig_patent_app_number] => 222822 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/222822
Digital signal processing apparatus and method therefor Dec 29, 1998 Issued
Array ( [id] => 1001535 [patent_doc_number] => 06912556 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-28 [patent_title] => 'Silicon averaging measurement circuit' [patent_app_type] => utility [patent_app_number] => 09/222953 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3233 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912556.pdf [firstpage_image] =>[orig_patent_app_number] => 09222953 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/222953
Silicon averaging measurement circuit Dec 29, 1998 Issued
Array ( [id] => 1480631 [patent_doc_number] => 06389442 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Efficient finite field multiplication in normal basis' [patent_app_type] => B1 [patent_app_number] => 09/221556 [patent_app_country] => US [patent_app_date] => 1998-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4424 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389442.pdf [firstpage_image] =>[orig_patent_app_number] => 09221556 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221556
Efficient finite field multiplication in normal basis Dec 27, 1998 Issued
Array ( [id] => 4380329 [patent_doc_number] => 06256656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Apparatus and method for extending computational precision of a computer system having a modular arithmetic processing unit' [patent_app_type] => 1 [patent_app_number] => 9/221911 [patent_app_country] => US [patent_app_date] => 1998-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9692 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256656.pdf [firstpage_image] =>[orig_patent_app_number] => 221911 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221911
Apparatus and method for extending computational precision of a computer system having a modular arithmetic processing unit Dec 27, 1998 Issued
Array ( [id] => 4423176 [patent_doc_number] => 06240432 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Enhanced random number generator' [patent_app_type] => 1 [patent_app_number] => 9/222271 [patent_app_country] => US [patent_app_date] => 1998-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1880 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240432.pdf [firstpage_image] =>[orig_patent_app_number] => 222271 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/222271
Enhanced random number generator Dec 27, 1998 Issued
Array ( [id] => 4297778 [patent_doc_number] => 06282558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Data processing system and register file' [patent_app_type] => 1 [patent_app_number] => 9/213369 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6558 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282558.pdf [firstpage_image] =>[orig_patent_app_number] => 213369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/213369
Data processing system and register file Dec 16, 1998 Issued
09/213260 A DATA PROCESSING DEVICE HAVING A CENTRAL PROCESSING UNIT AND DIGITAL SIGNAL PROCESSING UNIT Dec 16, 1998 Abandoned
Array ( [id] => 4235709 [patent_doc_number] => 06041340 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Method for configuring an FPGA for large FFTs and other vector rotation computations' [patent_app_type] => 1 [patent_app_number] => 9/211604 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4286 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041340.pdf [firstpage_image] =>[orig_patent_app_number] => 211604 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/211604
Method for configuring an FPGA for large FFTs and other vector rotation computations Dec 14, 1998 Issued
Array ( [id] => 4279808 [patent_doc_number] => 06260053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Efficient and scalable FIR filter architecture for decimation' [patent_app_type] => 1 [patent_app_number] => 9/208218 [patent_app_country] => US [patent_app_date] => 1998-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 7076 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260053.pdf [firstpage_image] =>[orig_patent_app_number] => 208218 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/208218
Efficient and scalable FIR filter architecture for decimation Dec 8, 1998 Issued
Array ( [id] => 1553635 [patent_doc_number] => 06347327 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Method and apparatus for N-nary incrementor' [patent_app_type] => B1 [patent_app_number] => 09/206830 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 9167 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347327.pdf [firstpage_image] =>[orig_patent_app_number] => 09206830 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206830
Method and apparatus for N-nary incrementor Dec 6, 1998 Issued
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