Search

Chuong D. Ngo

Examiner (ID: 8858, Phone: (571)272-3731 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2787, 2306, 2121, 2899, 2124, 2182, 2183, 2193
Total Applications
2158
Issued Applications
1754
Pending Applications
68
Abandoned Applications
343

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4267950 [patent_doc_number] => 06138134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Computational method and apparatus for finite field multiplication' [patent_app_type] => 1 [patent_app_number] => 9/157635 [patent_app_country] => US [patent_app_date] => 1998-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4369 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138134.pdf [firstpage_image] =>[orig_patent_app_number] => 157635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/157635
Computational method and apparatus for finite field multiplication Sep 20, 1998 Issued
Array ( [id] => 4278819 [patent_doc_number] => 06205461 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Floating point arithmetic logic unit leading zero count using fast approximate rounding' [patent_app_type] => 1 [patent_app_number] => 9/157090 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 7868 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205461.pdf [firstpage_image] =>[orig_patent_app_number] => 157090 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/157090
Floating point arithmetic logic unit leading zero count using fast approximate rounding Sep 17, 1998 Issued
Array ( [id] => 4315478 [patent_doc_number] => 06199089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Floating point arithmetic logic unit rounding using at least one least significant bit' [patent_app_type] => 1 [patent_app_number] => 9/156817 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 7934 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199089.pdf [firstpage_image] =>[orig_patent_app_number] => 156817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/156817
Floating point arithmetic logic unit rounding using at least one least significant bit Sep 17, 1998 Issued
Array ( [id] => 6412995 [patent_doc_number] => 20020038324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'SINC FILTER USING TWISTING SYMMETRY' [patent_app_type] => new [patent_app_number] => 09/153860 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 11567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20020038324.pdf [firstpage_image] =>[orig_patent_app_number] => 09153860 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/153860
Sinc filter using twisting symmetry Sep 15, 1998 Issued
Array ( [id] => 4334246 [patent_doc_number] => 06243733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Correct carry bit generation' [patent_app_type] => 1 [patent_app_number] => 9/153868 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 55 [patent_no_of_words] => 10884 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243733.pdf [firstpage_image] =>[orig_patent_app_number] => 153868 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/153868
Correct carry bit generation Sep 15, 1998 Issued
Array ( [id] => 4323076 [patent_doc_number] => 06189021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Method for forming two-dimensional discrete cosine transform and its inverse involving a reduced number of multiplication operations' [patent_app_type] => 1 [patent_app_number] => 9/153055 [patent_app_country] => US [patent_app_date] => 1998-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6870 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189021.pdf [firstpage_image] =>[orig_patent_app_number] => 153055 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/153055
Method for forming two-dimensional discrete cosine transform and its inverse involving a reduced number of multiplication operations Sep 14, 1998 Issued
Array ( [id] => 4370240 [patent_doc_number] => 06216146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method and apparatus for an N-nary adder gate' [patent_app_type] => 1 [patent_app_number] => 9/150829 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4274 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216146.pdf [firstpage_image] =>[orig_patent_app_number] => 150829 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150829
Method and apparatus for an N-nary adder gate Sep 9, 1998 Issued
Array ( [id] => 4269314 [patent_doc_number] => 06223199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method and apparatus for an N-NARY HPG gate' [patent_app_type] => 1 [patent_app_number] => 9/150575 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4909 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223199.pdf [firstpage_image] =>[orig_patent_app_number] => 150575 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150575
Method and apparatus for an N-NARY HPG gate Sep 9, 1998 Issued
Array ( [id] => 4175918 [patent_doc_number] => 06157938 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Fast fourier transform device with parallel lattice architecture' [patent_app_type] => 1 [patent_app_number] => 9/150964 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4964 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157938.pdf [firstpage_image] =>[orig_patent_app_number] => 150964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150964
Fast fourier transform device with parallel lattice architecture Sep 9, 1998 Issued
Array ( [id] => 4375431 [patent_doc_number] => 06219687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method and apparatus for an N-nary Sum/HPG gate' [patent_app_type] => 1 [patent_app_number] => 9/150720 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6188 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219687.pdf [firstpage_image] =>[orig_patent_app_number] => 150720 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150720
Method and apparatus for an N-nary Sum/HPG gate Sep 9, 1998 Issued
Array ( [id] => 4375415 [patent_doc_number] => 06219686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method and apparatus for an N-NARY sum/HPG adder/subtractor gate' [patent_app_type] => 1 [patent_app_number] => 9/150717 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 10217 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219686.pdf [firstpage_image] =>[orig_patent_app_number] => 150717 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150717
Method and apparatus for an N-NARY sum/HPG adder/subtractor gate Sep 9, 1998 Issued
Array ( [id] => 4178072 [patent_doc_number] => 06115726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Signal processor with local signal behavior' [patent_app_type] => 1 [patent_app_number] => 9/144360 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 54 [patent_no_of_words] => 26298 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115726.pdf [firstpage_image] =>[orig_patent_app_number] => 144360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/144360
Signal processor with local signal behavior Aug 30, 1998 Issued
Array ( [id] => 1538756 [patent_doc_number] => 06411976 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Efficient filter implementation' [patent_app_type] => B1 [patent_app_number] => 09/131929 [patent_app_country] => US [patent_app_date] => 1998-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 6792 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/411/06411976.pdf [firstpage_image] =>[orig_patent_app_number] => 09131929 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/131929
Efficient filter implementation Aug 9, 1998 Issued
Array ( [id] => 4056478 [patent_doc_number] => 05995988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Configurable parallel and bit serial load apparatus' [patent_app_type] => 1 [patent_app_number] => 9/131536 [patent_app_country] => US [patent_app_date] => 1998-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5434 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995988.pdf [firstpage_image] =>[orig_patent_app_number] => 131536 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/131536
Configurable parallel and bit serial load apparatus Aug 9, 1998 Issued
Array ( [id] => 4304086 [patent_doc_number] => 06269385 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Apparatus and method for performing rounding and addition in parallel in floating point multiplier' [patent_app_type] => 1 [patent_app_number] => 9/126441 [patent_app_country] => US [patent_app_date] => 1998-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6295 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269385.pdf [firstpage_image] =>[orig_patent_app_number] => 126441 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/126441
Apparatus and method for performing rounding and addition in parallel in floating point multiplier Jul 29, 1998 Issued
Array ( [id] => 4375372 [patent_doc_number] => 06219683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Radially distributed transverse filter' [patent_app_type] => 1 [patent_app_number] => 9/124129 [patent_app_country] => US [patent_app_date] => 1998-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1572 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219683.pdf [firstpage_image] =>[orig_patent_app_number] => 124129 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/124129
Radially distributed transverse filter Jul 28, 1998 Issued
Array ( [id] => 4238146 [patent_doc_number] => 06088714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Mechanism for calculating one-dimensional fast fourier transforms' [patent_app_type] => 1 [patent_app_number] => 9/123241 [patent_app_country] => US [patent_app_date] => 1998-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4777 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088714.pdf [firstpage_image] =>[orig_patent_app_number] => 123241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/123241
Mechanism for calculating one-dimensional fast fourier transforms Jul 26, 1998 Issued
Array ( [id] => 4421727 [patent_doc_number] => 06173302 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Decimation method and decimation filter' [patent_app_type] => 1 [patent_app_number] => 9/117318 [patent_app_country] => US [patent_app_date] => 1998-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3279 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173302.pdf [firstpage_image] =>[orig_patent_app_number] => 117318 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/117318
Decimation method and decimation filter Jul 26, 1998 Issued
Array ( [id] => 4236343 [patent_doc_number] => 06112217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method and apparatus for generating clock signals' [patent_app_type] => 1 [patent_app_number] => 9/122056 [patent_app_country] => US [patent_app_date] => 1998-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5465 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112217.pdf [firstpage_image] =>[orig_patent_app_number] => 122056 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/122056
Method and apparatus for generating clock signals Jul 23, 1998 Issued
Array ( [id] => 4146505 [patent_doc_number] => 06128638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method and apparatus for calculating X to the Exponent of Y' [patent_app_type] => 1 [patent_app_number] => 9/121157 [patent_app_country] => US [patent_app_date] => 1998-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7263 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128638.pdf [firstpage_image] =>[orig_patent_app_number] => 121157 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/121157
Method and apparatus for calculating X to the Exponent of Y Jul 22, 1998 Issued
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