Search

Chuong D. Ngo

Examiner (ID: 8858, Phone: (571)272-3731 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2787, 2306, 2121, 2899, 2124, 2182, 2183, 2193
Total Applications
2158
Issued Applications
1754
Pending Applications
68
Abandoned Applications
343

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4115408 [patent_doc_number] => 06067556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Method and apparatus for adding floating point numbers in a data processing system' [patent_app_type] => 1 [patent_app_number] => 9/013117 [patent_app_country] => US [patent_app_date] => 1998-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2746 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067556.pdf [firstpage_image] =>[orig_patent_app_number] => 013117 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/013117
Method and apparatus for adding floating point numbers in a data processing system Jan 25, 1998 Issued
Array ( [id] => 4159527 [patent_doc_number] => 06061707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method and apparatus for generating an end-around carry in a floating-point pipeline within a computer system' [patent_app_type] => 1 [patent_app_number] => 9/008462 [patent_app_country] => US [patent_app_date] => 1998-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3865 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061707.pdf [firstpage_image] =>[orig_patent_app_number] => 008462 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/008462
Method and apparatus for generating an end-around carry in a floating-point pipeline within a computer system Jan 15, 1998 Issued
Array ( [id] => 4063136 [patent_doc_number] => 05964826 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Division circuits based on power-sum circuit for finite field GF(2.sup.m)' [patent_app_type] => 1 [patent_app_number] => 9/006424 [patent_app_country] => US [patent_app_date] => 1998-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6488 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/964/05964826.pdf [firstpage_image] =>[orig_patent_app_number] => 006424 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/006424
Division circuits based on power-sum circuit for finite field GF(2.sup.m) Jan 12, 1998 Issued
Array ( [id] => 4020667 [patent_doc_number] => 05987483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Random number generator based on directional randomness associated with naturally occurring random events, and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/005089 [patent_app_country] => US [patent_app_date] => 1998-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2789 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987483.pdf [firstpage_image] =>[orig_patent_app_number] => 005089 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/005089
Random number generator based on directional randomness associated with naturally occurring random events, and method therefor Jan 8, 1998 Issued
Array ( [id] => 4151705 [patent_doc_number] => 06148319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Multiplier' [patent_app_type] => 1 [patent_app_number] => 9/004872 [patent_app_country] => US [patent_app_date] => 1998-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1661 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148319.pdf [firstpage_image] =>[orig_patent_app_number] => 004872 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/004872
Multiplier Jan 8, 1998 Issued
Array ( [id] => 3996399 [patent_doc_number] => 05961574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Device for obtaining positional information' [patent_app_type] => 1 [patent_app_number] => 9/004675 [patent_app_country] => US [patent_app_date] => 1998-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2993 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961574.pdf [firstpage_image] =>[orig_patent_app_number] => 004675 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/004675
Device for obtaining positional information Jan 7, 1998 Issued
Array ( [id] => 1297765 [patent_doc_number] => 06631393 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Method and apparatus for speculative addition using a limited carry' [patent_app_type] => B1 [patent_app_number] => 09/002173 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3401 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631393.pdf [firstpage_image] =>[orig_patent_app_number] => 09002173 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002173
Method and apparatus for speculative addition using a limited carry Dec 30, 1997 Issued
Array ( [id] => 3969501 [patent_doc_number] => 05991787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Reducing peak spectral error in inverse Fast Fourier Transform using MMX.TM. technology' [patent_app_type] => 1 [patent_app_number] => 9/002292 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 13843 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991787.pdf [firstpage_image] =>[orig_patent_app_number] => 002292 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002292
Reducing peak spectral error in inverse Fast Fourier Transform using MMX.TM. technology Dec 30, 1997 Issued
Array ( [id] => 4113923 [patent_doc_number] => 06049816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Pipeline stop circuit for external memory access' [patent_app_type] => 1 [patent_app_number] => 9/001010 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 42 [patent_no_of_words] => 4246 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049816.pdf [firstpage_image] =>[orig_patent_app_number] => 001010 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001010
Pipeline stop circuit for external memory access Dec 29, 1997 Issued
Array ( [id] => 4323923 [patent_doc_number] => 06327601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Linear transform system for decoding video data' [patent_app_type] => 1 [patent_app_number] => 9/001050 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3678 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327601.pdf [firstpage_image] =>[orig_patent_app_number] => 001050 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001050
Linear transform system for decoding video data Dec 29, 1997 Issued
Array ( [id] => 3970119 [patent_doc_number] => 05999957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Lossless transform coding system for digital signals' [patent_app_type] => 1 [patent_app_number] => 8/999397 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6431 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999957.pdf [firstpage_image] =>[orig_patent_app_number] => 999397 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/999397
Lossless transform coding system for digital signals Dec 28, 1997 Issued
Array ( [id] => 3969484 [patent_doc_number] => 05991786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Circuit and method for shifting or rotating operands of multiple size' [patent_app_type] => 1 [patent_app_number] => 8/995259 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7257 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991786.pdf [firstpage_image] =>[orig_patent_app_number] => 995259 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/995259
Circuit and method for shifting or rotating operands of multiple size Dec 18, 1997 Issued
Array ( [id] => 6143278 [patent_doc_number] => 20020002574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'VIDEO FRAME RENDERING ENGINE' [patent_app_type] => new [patent_app_number] => 08/993442 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11274 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20020002574.pdf [firstpage_image] =>[orig_patent_app_number] => 08993442 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993442
Video frame rendering engine Dec 17, 1997 Issued
Array ( [id] => 3969544 [patent_doc_number] => 05991789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Circuit arrangement for realizing logic elements that can be represented by threshold value equations' [patent_app_type] => 1 [patent_app_number] => 8/981664 [patent_app_country] => US [patent_app_date] => 1997-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7373 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991789.pdf [firstpage_image] =>[orig_patent_app_number] => 981664 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/981664
Circuit arrangement for realizing logic elements that can be represented by threshold value equations Dec 3, 1997 Issued
Array ( [id] => 3774665 [patent_doc_number] => 05844829 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Configurable parallel and bit serial load apparatus' [patent_app_type] => 1 [patent_app_number] => 8/985392 [patent_app_country] => US [patent_app_date] => 1997-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5467 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844829.pdf [firstpage_image] =>[orig_patent_app_number] => 985392 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/985392
Configurable parallel and bit serial load apparatus Dec 3, 1997 Issued
Array ( [id] => 4198031 [patent_doc_number] => 06038576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Bit-depth increase by bit replication' [patent_app_type] => 1 [patent_app_number] => 8/982954 [patent_app_country] => US [patent_app_date] => 1997-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 4866 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038576.pdf [firstpage_image] =>[orig_patent_app_number] => 982954 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982954
Bit-depth increase by bit replication Dec 1, 1997 Issued
Array ( [id] => 3969372 [patent_doc_number] => 05957996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Digital data comparator and microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/982299 [patent_app_country] => US [patent_app_date] => 1997-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5718 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/957/05957996.pdf [firstpage_image] =>[orig_patent_app_number] => 982299 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982299
Digital data comparator and microprocessor Nov 30, 1997 Issued
Array ( [id] => 3939504 [patent_doc_number] => 05954787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Method of generating sine/cosine function and apparatus using the same for use in digital signal processor' [patent_app_type] => 1 [patent_app_number] => 8/982281 [patent_app_country] => US [patent_app_date] => 1997-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4540 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/954/05954787.pdf [firstpage_image] =>[orig_patent_app_number] => 982281 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982281
Method of generating sine/cosine function and apparatus using the same for use in digital signal processor Nov 30, 1997 Issued
Array ( [id] => 4103039 [patent_doc_number] => 06026421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Apparatus for multiprecision integer arithmetic' [patent_app_type] => 1 [patent_app_number] => 8/979803 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 11902 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026421.pdf [firstpage_image] =>[orig_patent_app_number] => 979803 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979803
Apparatus for multiprecision integer arithmetic Nov 25, 1997 Issued
Array ( [id] => 4380267 [patent_doc_number] => 06256652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Binary code compression and decompression and parallel compression and decompression processor' [patent_app_type] => 1 [patent_app_number] => 8/952039 [patent_app_country] => US [patent_app_date] => 1997-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2860 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256652.pdf [firstpage_image] =>[orig_patent_app_number] => 952039 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/952039
Binary code compression and decompression and parallel compression and decompression processor Nov 5, 1997 Issued
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