Search

Chuong D. Ngo

Examiner (ID: 8858, Phone: (571)272-3731 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2787, 2306, 2121, 2899, 2124, 2182, 2183, 2193
Total Applications
2158
Issued Applications
1754
Pending Applications
68
Abandoned Applications
343

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4151679 [patent_doc_number] => 06148318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Square root extraction circuit and floating-point square root extraction device' [patent_app_type] => 1 [patent_app_number] => 8/964888 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 15835 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148318.pdf [firstpage_image] =>[orig_patent_app_number] => 964888 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964888
Square root extraction circuit and floating-point square root extraction device Nov 4, 1997 Issued
Array ( [id] => 4178089 [patent_doc_number] => 06115727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Time-weighted trimmed-mean filtering apparatus and method' [patent_app_type] => 1 [patent_app_number] => 8/961480 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4873 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115727.pdf [firstpage_image] =>[orig_patent_app_number] => 961480 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/961480
Time-weighted trimmed-mean filtering apparatus and method Oct 30, 1997 Issued
08/960957 INTEGRATED FILTER AND DETECTION PROCESS Oct 29, 1997 Abandoned
Array ( [id] => 4225141 [patent_doc_number] => 06029187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Fast regular multiplier architecture' [patent_app_type] => 1 [patent_app_number] => 8/959245 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6508 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 576 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029187.pdf [firstpage_image] =>[orig_patent_app_number] => 959245 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959245
Fast regular multiplier architecture Oct 27, 1997 Issued
Array ( [id] => 3896151 [patent_doc_number] => 05894426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Maximum/minimum value determination apparatus' [patent_app_type] => 1 [patent_app_number] => 8/959451 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1577 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894426.pdf [firstpage_image] =>[orig_patent_app_number] => 959451 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959451
Maximum/minimum value determination apparatus Oct 27, 1997 Issued
Array ( [id] => 4004704 [patent_doc_number] => 05892695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Sample rate conversion' [patent_app_type] => 1 [patent_app_number] => 8/959348 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2338 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892695.pdf [firstpage_image] =>[orig_patent_app_number] => 959348 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959348
Sample rate conversion Oct 27, 1997 Issued
Array ( [id] => 4254029 [patent_doc_number] => 06119139 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Virtual windowing for fixed-point digital signal processors' [patent_app_type] => 1 [patent_app_number] => 8/959461 [patent_app_country] => US [patent_app_date] => 1997-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1922 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119139.pdf [firstpage_image] =>[orig_patent_app_number] => 959461 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959461
Virtual windowing for fixed-point digital signal processors Oct 26, 1997 Issued
Array ( [id] => 1532884 [patent_doc_number] => 06480875 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Adder circuit and associated layout structure' [patent_app_type] => B1 [patent_app_number] => 08/957159 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7256 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480875.pdf [firstpage_image] =>[orig_patent_app_number] => 08957159 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/957159
Adder circuit and associated layout structure Oct 23, 1997 Issued
Array ( [id] => 4272757 [patent_doc_number] => 06209014 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Look-ahead LMS technique' [patent_app_type] => 1 [patent_app_number] => 8/955415 [patent_app_country] => US [patent_app_date] => 1997-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2449 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209014.pdf [firstpage_image] =>[orig_patent_app_number] => 955415 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/955415
Look-ahead LMS technique Oct 20, 1997 Issued
Array ( [id] => 3960451 [patent_doc_number] => 05974436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Execution processor for carrying out power calculation' [patent_app_type] => 1 [patent_app_number] => 8/954586 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 19477 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974436.pdf [firstpage_image] =>[orig_patent_app_number] => 954586 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/954586
Execution processor for carrying out power calculation Oct 19, 1997 Issued
Array ( [id] => 3970091 [patent_doc_number] => 05999955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Delay generation filter' [patent_app_type] => 1 [patent_app_number] => 8/954702 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3890 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999955.pdf [firstpage_image] =>[orig_patent_app_number] => 954702 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/954702
Delay generation filter Oct 19, 1997 Issued
Array ( [id] => 3915378 [patent_doc_number] => 05951626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Adaptive filter' [patent_app_type] => 1 [patent_app_number] => 8/953120 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3017 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951626.pdf [firstpage_image] =>[orig_patent_app_number] => 953120 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/953120
Adaptive filter Oct 16, 1997 Issued
Array ( [id] => 4150883 [patent_doc_number] => 06035315 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Floating point power conservation' [patent_app_type] => 1 [patent_app_number] => 8/953034 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2647 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035315.pdf [firstpage_image] =>[orig_patent_app_number] => 953034 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/953034
Floating point power conservation Oct 16, 1997 Issued
Array ( [id] => 4084388 [patent_doc_number] => 06009445 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Reconfigurable infinite impulse response digital filter' [patent_app_type] => 1 [patent_app_number] => 8/950730 [patent_app_country] => US [patent_app_date] => 1997-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1726 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009445.pdf [firstpage_image] =>[orig_patent_app_number] => 950730 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/950730
Reconfigurable infinite impulse response digital filter Oct 14, 1997 Issued
Array ( [id] => 4027071 [patent_doc_number] => 05907500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Motion compensation adder for decoding/decompressing compressed moving pictures' [patent_app_type] => 1 [patent_app_number] => 8/950834 [patent_app_country] => US [patent_app_date] => 1997-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6663 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907500.pdf [firstpage_image] =>[orig_patent_app_number] => 950834 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/950834
Motion compensation adder for decoding/decompressing compressed moving pictures Oct 14, 1997 Issued
Array ( [id] => 3980420 [patent_doc_number] => 05886916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Analog multiplier' [patent_app_type] => 1 [patent_app_number] => 8/949184 [patent_app_country] => US [patent_app_date] => 1997-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4584 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886916.pdf [firstpage_image] =>[orig_patent_app_number] => 949184 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/949184
Analog multiplier Oct 9, 1997 Issued
Array ( [id] => 4077252 [patent_doc_number] => 05867408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Process and device with digital signal processor for the implementation of a viterbi algorithm' [patent_app_type] => 1 [patent_app_number] => 8/942735 [patent_app_country] => US [patent_app_date] => 1997-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2454 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867408.pdf [firstpage_image] =>[orig_patent_app_number] => 942735 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942735
Process and device with digital signal processor for the implementation of a viterbi algorithm Oct 1, 1997 Issued
Array ( [id] => 3915406 [patent_doc_number] => 05951628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Method and system for performing a convolution operation' [patent_app_type] => 1 [patent_app_number] => 8/939497 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 28 [patent_no_of_words] => 17647 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951628.pdf [firstpage_image] =>[orig_patent_app_number] => 939497 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/939497
Method and system for performing a convolution operation Sep 28, 1997 Issued
Array ( [id] => 4199248 [patent_doc_number] => 06021423 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Method for parallel-efficient configuring an FPGA for large FFTS and other vector rotation computations' [patent_app_type] => 1 [patent_app_number] => 8/937977 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3564 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021423.pdf [firstpage_image] =>[orig_patent_app_number] => 937977 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/937977
Method for parallel-efficient configuring an FPGA for large FFTS and other vector rotation computations Sep 25, 1997 Issued
Array ( [id] => 4005055 [patent_doc_number] => 05920497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Method and apparatus for performing a double precision operation using a single instruction type' [patent_app_type] => 1 [patent_app_number] => 8/926949 [patent_app_country] => US [patent_app_date] => 1997-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1957 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920497.pdf [firstpage_image] =>[orig_patent_app_number] => 926949 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/926949
Method and apparatus for performing a double precision operation using a single instruction type Sep 9, 1997 Issued
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