Search

Chuong D. Ngo

Examiner (ID: 8858, Phone: (571)272-3731 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2787, 2306, 2121, 2899, 2124, 2182, 2183, 2193
Total Applications
2158
Issued Applications
1754
Pending Applications
68
Abandoned Applications
343

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3936901 [patent_doc_number] => 05946222 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Method and apparatus for performing a masked byte addition operation' [patent_app_type] => 1 [patent_app_number] => 8/770457 [patent_app_country] => US [patent_app_date] => 1996-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3421 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946222.pdf [firstpage_image] =>[orig_patent_app_number] => 770457 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/770457
Method and apparatus for performing a masked byte addition operation Dec 19, 1996 Issued
Array ( [id] => 3751873 [patent_doc_number] => 05787024 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Horizontal filter in moving picture decoding apparatus' [patent_app_type] => 1 [patent_app_number] => 8/760297 [patent_app_country] => US [patent_app_date] => 1996-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2222 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787024.pdf [firstpage_image] =>[orig_patent_app_number] => 760297 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/760297
Horizontal filter in moving picture decoding apparatus Dec 3, 1996 Issued
Array ( [id] => 3809045 [patent_doc_number] => 05828590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Multiplier based on a variable radix multiplier coding' [patent_app_type] => 1 [patent_app_number] => 8/758633 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7604 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 530 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828590.pdf [firstpage_image] =>[orig_patent_app_number] => 758633 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/758633
Multiplier based on a variable radix multiplier coding Nov 26, 1996 Issued
Array ( [id] => 3712722 [patent_doc_number] => 05675526 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Processor performing packed data multiplication' [patent_app_type] => 1 [patent_app_number] => 8/756708 [patent_app_country] => US [patent_app_date] => 1996-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7094 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675526.pdf [firstpage_image] =>[orig_patent_app_number] => 756708 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/756708
Processor performing packed data multiplication Nov 25, 1996 Issued
Array ( [id] => 4084468 [patent_doc_number] => 06009451 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Method for generating barrel shifter result flags directly from input data' [patent_app_type] => 1 [patent_app_number] => 8/754430 [patent_app_country] => US [patent_app_date] => 1996-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7218 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009451.pdf [firstpage_image] =>[orig_patent_app_number] => 754430 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/754430
Method for generating barrel shifter result flags directly from input data Nov 21, 1996 Issued
Array ( [id] => 3697821 [patent_doc_number] => 05691929 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => '90-degree phase shift network, system for controlling a 90-degree phase shift characteristic of the network, linearizer using all-pass filters, and system for controlling the linearizer' [patent_app_type] => 1 [patent_app_number] => 8/754583 [patent_app_country] => US [patent_app_date] => 1996-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 6814 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691929.pdf [firstpage_image] =>[orig_patent_app_number] => 754583 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/754583
90-degree phase shift network, system for controlling a 90-degree phase shift characteristic of the network, linearizer using all-pass filters, and system for controlling the linearizer Nov 20, 1996 Issued
Array ( [id] => 3741759 [patent_doc_number] => 05694347 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Digital signal processing system' [patent_app_type] => 1 [patent_app_number] => 8/752773 [patent_app_country] => US [patent_app_date] => 1996-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 4714 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694347.pdf [firstpage_image] =>[orig_patent_app_number] => 752773 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/752773
Digital signal processing system Nov 19, 1996 Issued
Array ( [id] => 3922829 [patent_doc_number] => 05928316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Fused floating-point multiply-and-accumulate unit with carry correction' [patent_app_type] => 1 [patent_app_number] => 8/751563 [patent_app_country] => US [patent_app_date] => 1996-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7879 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/928/05928316.pdf [firstpage_image] =>[orig_patent_app_number] => 751563 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/751563
Fused floating-point multiply-and-accumulate unit with carry correction Nov 17, 1996 Issued
Array ( [id] => 3873130 [patent_doc_number] => 05796644 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Floating-point multiply-and-accumulate unit with classes for alignment and normalization' [patent_app_type] => 1 [patent_app_number] => 8/746828 [patent_app_country] => US [patent_app_date] => 1996-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 8362 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796644.pdf [firstpage_image] =>[orig_patent_app_number] => 746828 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/746828
Floating-point multiply-and-accumulate unit with classes for alignment and normalization Nov 17, 1996 Issued
Array ( [id] => 4012065 [patent_doc_number] => 05993051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Combined leading one and leading zero anticipator' [patent_app_type] => 1 [patent_app_number] => 8/746880 [patent_app_country] => US [patent_app_date] => 1996-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5536 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/993/05993051.pdf [firstpage_image] =>[orig_patent_app_number] => 746880 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/746880
Combined leading one and leading zero anticipator Nov 17, 1996 Issued
Array ( [id] => 3732939 [patent_doc_number] => 05673215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Non-restoring fixed-point divider apparatus' [patent_app_type] => 1 [patent_app_number] => 8/746708 [patent_app_country] => US [patent_app_date] => 1996-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3779 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/673/05673215.pdf [firstpage_image] =>[orig_patent_app_number] => 746708 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/746708
Non-restoring fixed-point divider apparatus Nov 14, 1996 Issued
Array ( [id] => 3969426 [patent_doc_number] => 05958000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Two-bit booth multiplier with reduced data path width' [patent_app_type] => 1 [patent_app_number] => 8/751525 [patent_app_country] => US [patent_app_date] => 1996-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5159 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958000.pdf [firstpage_image] =>[orig_patent_app_number] => 751525 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/751525
Two-bit booth multiplier with reduced data path width Nov 14, 1996 Issued
Array ( [id] => 4050842 [patent_doc_number] => 06007232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Calculating the average of two integer numbers rounded towards zero in a single instruction cycle' [patent_app_type] => 1 [patent_app_number] => 8/748851 [patent_app_country] => US [patent_app_date] => 1996-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4301 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/007/06007232.pdf [firstpage_image] =>[orig_patent_app_number] => 748851 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/748851
Calculating the average of two integer numbers rounded towards zero in a single instruction cycle Nov 13, 1996 Issued
Array ( [id] => 3988382 [patent_doc_number] => 05917739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Calculating the average of four integer numbers rounded towards zero in a single instruction cycle' [patent_app_type] => 1 [patent_app_number] => 8/748873 [patent_app_country] => US [patent_app_date] => 1996-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5176 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917739.pdf [firstpage_image] =>[orig_patent_app_number] => 748873 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/748873
Calculating the average of four integer numbers rounded towards zero in a single instruction cycle Nov 13, 1996 Issued
Array ( [id] => 3797784 [patent_doc_number] => 05822231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Ternary based shifter that supports multiple data types for shift functions' [patent_app_type] => 1 [patent_app_number] => 8/741991 [patent_app_country] => US [patent_app_date] => 1996-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4515 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822231.pdf [firstpage_image] =>[orig_patent_app_number] => 741991 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/741991
Ternary based shifter that supports multiple data types for shift functions Oct 30, 1996 Issued
Array ( [id] => 4010380 [patent_doc_number] => 05923577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Method and apparatus for generating an initial estimate for a floating point reciprocal' [patent_app_type] => 1 [patent_app_number] => 8/729661 [patent_app_country] => US [patent_app_date] => 1996-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5988 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923577.pdf [firstpage_image] =>[orig_patent_app_number] => 729661 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/729661
Method and apparatus for generating an initial estimate for a floating point reciprocal Oct 20, 1996 Issued
Array ( [id] => 4054156 [patent_doc_number] => 05909382 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Tablet with system power saving features including reactivation by pencontact after inactive period' [patent_app_type] => 1 [patent_app_number] => 8/734221 [patent_app_country] => US [patent_app_date] => 1996-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4462 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909382.pdf [firstpage_image] =>[orig_patent_app_number] => 734221 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/734221
Tablet with system power saving features including reactivation by pencontact after inactive period Oct 20, 1996 Issued
Array ( [id] => 4026909 [patent_doc_number] => 05880985 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Efficient combined array for 2n bit n bit multiplications' [patent_app_type] => 1 [patent_app_number] => 8/735058 [patent_app_country] => US [patent_app_date] => 1996-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4694 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880985.pdf [firstpage_image] =>[orig_patent_app_number] => 735058 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/735058
Efficient combined array for 2n bit n bit multiplications Oct 17, 1996 Issued
Array ( [id] => 4251766 [patent_doc_number] => 06076098 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Adder for generating sum and sum plus one in parallel' [patent_app_type] => 1 [patent_app_number] => 8/730921 [patent_app_country] => US [patent_app_date] => 1996-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 3163 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076098.pdf [firstpage_image] =>[orig_patent_app_number] => 730921 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/730921
Adder for generating sum and sum plus one in parallel Oct 17, 1996 Issued
Array ( [id] => 3774623 [patent_doc_number] => 05844826 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Leading zero count circuit' [patent_app_type] => 1 [patent_app_number] => 8/730922 [patent_app_country] => US [patent_app_date] => 1996-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 5371 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844826.pdf [firstpage_image] =>[orig_patent_app_number] => 730922 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/730922
Leading zero count circuit Oct 17, 1996 Issued
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