Search

Chuong D. Ngo

Examiner (ID: 8858, Phone: (571)272-3731 , Office: P/2182 )

Most Active Art Unit
2193
Art Unit(s)
2787, 2306, 2121, 2899, 2124, 2182, 2183, 2193
Total Applications
2158
Issued Applications
1754
Pending Applications
68
Abandoned Applications
343

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13361339 [patent_doc_number] => 20180232209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => TRANSPOSING IN A MATRIX-VECTOR PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/896301 [patent_app_country] => US [patent_app_date] => 2018-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10902 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15896301 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/896301
Transposing in a matrix-vector processor Feb 13, 2018 Issued
Array ( [id] => 17492130 [patent_doc_number] => 11281433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Method for generating a prime number by testing co-primalty between a prime candidate and a predetermined prime number in a binary base [patent_app_type] => utility [patent_app_number] => 16/486904 [patent_app_country] => US [patent_app_date] => 2018-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4310 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 458 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16486904 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/486904
Method for generating a prime number by testing co-primalty between a prime candidate and a predetermined prime number in a binary base Feb 8, 2018 Issued
Array ( [id] => 16592821 [patent_doc_number] => 10902086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Subspace-constrained partial update method for high-dimensional adaptive processing systems [patent_app_type] => utility [patent_app_number] => 15/883359 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 12063 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15883359 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/883359
Subspace-constrained partial update method for high-dimensional adaptive processing systems Jan 29, 2018 Issued
Array ( [id] => 17907579 [patent_doc_number] => 11461433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Error correction in computation [patent_app_type] => utility [patent_app_number] => 16/475297 [patent_app_country] => US [patent_app_date] => 2018-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 11769 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16475297 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/475297
Error correction in computation Jan 9, 2018 Issued
Array ( [id] => 12914389 [patent_doc_number] => 20180196639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => DATA PROCESSING DEVICE, DATA PROCESSING METHOD, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 15/863242 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863242 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/863242
Data processing device, data processing method, and storage medium Jan 4, 2018 Issued
Array ( [id] => 14857153 [patent_doc_number] => 10417304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Dual phase matrix-vector multiplication system [patent_app_type] => utility [patent_app_number] => 15/843283 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10799 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15843283 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/843283
Dual phase matrix-vector multiplication system Dec 14, 2017 Issued
Array ( [id] => 16263733 [patent_doc_number] => 10755169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Hybrid non-uniform convolution transform engine for deep learning applications [patent_app_type] => utility [patent_app_number] => 15/841733 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4678 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841733 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/841733
Hybrid non-uniform convolution transform engine for deep learning applications Dec 13, 2017 Issued
Array ( [id] => 14188875 [patent_doc_number] => 20190114143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => RANDOM NUMBER GENERATING SYSTEM AND RANDOM NUMBER GENERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/842833 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15842833 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/842833
Random number generating system and random number generating method thereof Dec 13, 2017 Issued
Array ( [id] => 13906667 [patent_doc_number] => 20190042538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => ACCELERATOR FOR PROCESSING DATA [patent_app_type] => utility [patent_app_number] => 15/840552 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840552 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/840552
Accelerator for processing data Dec 12, 2017 Issued
Array ( [id] => 12628650 [patent_doc_number] => 20180101380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => DETECTION OF POTENTIAL NEED TO USE A LARGER DATA FORMAT IN PERFORMING FLOATING POINT OPERATIONS [patent_app_type] => utility [patent_app_number] => 15/839261 [patent_app_country] => US [patent_app_date] => 2017-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15839261 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/839261
Detection of potential need to use a larger data format in performing floating point operations Dec 11, 2017 Issued
Array ( [id] => 14444617 [patent_doc_number] => 20190180182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => Activation Function Functional Block for Electronic Devices [patent_app_type] => utility [patent_app_number] => 15/836080 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15836080 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/836080
Activation function functional block for electronic devices Dec 7, 2017 Issued
Array ( [id] => 14380261 [patent_doc_number] => 20190164043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => LOW-POWER HARDWARE ACCELERATION METHOD AND SYSTEM FOR CONVOLUTION NEURAL NETWORK COMPUTATION [patent_app_type] => utility [patent_app_number] => 15/823091 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15823091 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/823091
Low-power hardware acceleration method and system for convolution neural network computation Nov 26, 2017 Issued
Array ( [id] => 12756322 [patent_doc_number] => 20180143941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => METHOD OF SOLVING STRESS BASED ON FORCE BOUNDARY AND BALANCE CONDITION [patent_app_type] => utility [patent_app_number] => 15/820392 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15820392 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/820392
METHOD OF SOLVING STRESS BASED ON FORCE BOUNDARY AND BALANCE CONDITION Nov 20, 2017 Abandoned
Array ( [id] => 12617367 [patent_doc_number] => 20180097619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => INSTRUCTION FOR PERFORMING A PSEUDORANDOM NUMBER SEED OPERATION [patent_app_type] => utility [patent_app_number] => 15/819459 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819459 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/819459
Instruction for performing a pseudorandom number seed operation Nov 20, 2017 Issued
Array ( [id] => 13596453 [patent_doc_number] => 20180349775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => REAL TIME COGNITIVE REASONING USING A CIRCUIT WITH VARYING CONFIDENCE LEVEL ALERTS [patent_app_type] => utility [patent_app_number] => 15/818977 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15818977 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/818977
Real time cognitive reasoning using a circuit with varying confidence level alerts Nov 20, 2017 Issued
Array ( [id] => 13738063 [patent_doc_number] => 20180373500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => COMPILER CONTROLS FOR PROGRAM LANGUAGE CONSTRUCTS [patent_app_type] => utility [patent_app_number] => 15/816384 [patent_app_country] => US [patent_app_date] => 2017-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15816384 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/816384
Compiler controls for program language constructs Nov 16, 2017 Issued
Array ( [id] => 12531903 [patent_doc_number] => 10007488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Secured pseudo-random number generator [patent_app_type] => utility [patent_app_number] => 15/813286 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6420 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813286 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813286
Secured pseudo-random number generator Nov 14, 2017 Issued
Array ( [id] => 12868597 [patent_doc_number] => 20180181374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => APPARATUS AND METHOD FOR MODULAR MULTIPLICATION [patent_app_type] => utility [patent_app_number] => 15/807888 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15807888 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/807888
Apparatus and method for modular multiplication Nov 8, 2017 Issued
Array ( [id] => 12712927 [patent_doc_number] => 20180129475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => BIT-SERIAL MULTIPLIER FOR FPGA APPLICATIONS [patent_app_type] => utility [patent_app_number] => 15/807147 [patent_app_country] => US [patent_app_date] => 2017-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15807147 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/807147
Bit-serial multiplier for FPGA applications Nov 7, 2017 Issued
Array ( [id] => 14061689 [patent_doc_number] => 10235137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Decimal shift and divide instruction [patent_app_type] => utility [patent_app_number] => 15/806862 [patent_app_country] => US [patent_app_date] => 2017-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 9564 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15806862 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/806862
Decimal shift and divide instruction Nov 7, 2017 Issued
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