Search

Clare E. Heflin

Examiner (ID: 10900, Phone: (571)272-2604 , Office: P/2911 )

Most Active Art Unit
2911
Art Unit(s)
2911
Total Applications
5735
Issued Applications
5670
Pending Applications
1
Abandoned Applications
64

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20208553 [patent_doc_number] => 20250278273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => ASYNCHRONOUS RELEASE OPERATIONS IN A MULTIPROCESSOR SYSTEM [patent_app_type] => utility [patent_app_number] => 18/593817 [patent_app_country] => US [patent_app_date] => 2024-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18593817 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/593817
ASYNCHRONOUS RELEASE OPERATIONS IN A MULTIPROCESSOR SYSTEM Feb 29, 2024 Pending
Array ( [id] => 20195394 [patent_doc_number] => 20250272104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => SWITCHING A PREDICTED BRANCH TYPE FOLLOWING A MISPREDICTION OF A NUMBER OF LOOP ITERATIONS [patent_app_type] => utility [patent_app_number] => 18/588615 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18588615 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/588615
Switching a predicted branch type following a misprediction of a number of loop iterations Feb 26, 2024 Issued
Array ( [id] => 19334283 [patent_doc_number] => 20240248713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => VECTOR PROCESSOR PERFORMING VECTOR AND ELEMENT REDUCTION METHOD WITH SAME CIRCUIT STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/582614 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18582614 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/582614
VECTOR PROCESSOR PERFORMING VECTOR AND ELEMENT REDUCTION METHOD WITH SAME CIRCUIT STRUCTURE Feb 19, 2024 Pending
Array ( [id] => 19718826 [patent_doc_number] => 12204363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network [patent_app_type] => utility [patent_app_number] => 18/412846 [patent_app_country] => US [patent_app_date] => 2024-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 48 [patent_no_of_words] => 60845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412846 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/412846
System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network Jan 14, 2024 Issued
Array ( [id] => 19129219 [patent_doc_number] => 20240134572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => ALLOCATION OF MEMORY BY MAPPING REGISTERS REFERENCED BY DIFFERENT INSTANCES OF A TASK TO INDIVIDUAL LOGICAL MEMORIES [patent_app_type] => utility [patent_app_number] => 18/401558 [patent_app_country] => US [patent_app_date] => 2023-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401558 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/401558
ALLOCATION OF MEMORY BY MAPPING REGISTERS REFERENCED BY DIFFERENT INSTANCES OF A TASK TO INDIVIDUAL LOGICAL MEMORIES Dec 30, 2023 Pending
Array ( [id] => 20070656 [patent_doc_number] => 20250208878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => ACCUMULATION APERTURES [patent_app_type] => utility [patent_app_number] => 18/390821 [patent_app_country] => US [patent_app_date] => 2023-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18390821 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/390821
ACCUMULATION APERTURES Dec 19, 2023 Pending
Array ( [id] => 20051997 [patent_doc_number] => 20250190219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => MAINTAINING APPROXIMATE UNIFORMITY OF AGING OF EQUIVALENT PROCESSING CIRCUITS IN A PIPELINE STAGE(S) IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/533711 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18533711 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/533711
Maintaining approximate uniformity of aging of equivalent processing circuits in a pipeline stage(s) in a processor Dec 7, 2023 Issued
Array ( [id] => 19283780 [patent_doc_number] => 20240220256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => POLYMORPHIC TWO-DIMENSIONAL REGISTER FILE [patent_app_type] => utility [patent_app_number] => 18/525217 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18525217 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/525217
POLYMORPHIC TWO-DIMENSIONAL REGISTER FILE Nov 29, 2023 Abandoned
Array ( [id] => 19347319 [patent_doc_number] => 20240256282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => IN-ORDER PROCESSOR USING MULTIPLE-ISSUE SCHEME AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/516513 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18516513 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/516513
IN-ORDER PROCESSOR USING MULTIPLE-ISSUE SCHEME AND METHOD OF OPERATING THE SAME Nov 20, 2023 Pending
Array ( [id] => 18941737 [patent_doc_number] => 20240036876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => PIPELINE PROTECTION FOR CPUS WITH SAVE AND RESTORE OF INTERMEDIATE RESULTS [patent_app_type] => utility [patent_app_number] => 18/487186 [patent_app_country] => US [patent_app_date] => 2023-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18487186 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/487186
CPUs with capture queues to save and restore intermediate results and out-of-order results Oct 15, 2023 Issued
Array ( [id] => 20087209 [patent_doc_number] => 20250217145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => TECHNIQUES FOR PIPELINING SINGLE THREAD INSTRUCTIONS TO IMPROVE EXECUTION TIME [patent_app_type] => utility [patent_app_number] => 18/550566 [patent_app_country] => US [patent_app_date] => 2023-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18550566 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/550566
TECHNIQUES FOR PIPELINING SINGLE THREAD INSTRUCTIONS TO IMPROVE EXECUTION TIME Sep 6, 2023 Pending
Array ( [id] => 19340725 [patent_doc_number] => 12050918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Coprocessor prefetcher [patent_app_type] => utility [patent_app_number] => 18/361244 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12497 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361244
Coprocessor prefetcher Jul 27, 2023 Issued
Array ( [id] => 20215035 [patent_doc_number] => 12411688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Gather buffer management for unaligned and gather load operations [patent_app_type] => utility [patent_app_number] => 18/225911 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5142 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225911 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/225911
Gather buffer management for unaligned and gather load operations Jul 24, 2023 Issued
Array ( [id] => 19711374 [patent_doc_number] => 20250021516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => SINGLE INSTRUCTION MULTIPLE DISPATCHES FOR SHORT KERNELS IN A RECONFIGURABLE PARALLEL PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/220169 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220169 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/220169
SINGLE INSTRUCTION MULTIPLE DISPATCHES FOR SHORT KERNELS IN A RECONFIGURABLE PARALLEL PROCESSOR Jul 9, 2023 Pending
Array ( [id] => 19971605 [patent_doc_number] => 12340220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Register mapping to map architectural registers to corresponding physical registers based on a mode indicating a register length [patent_app_type] => utility [patent_app_number] => 18/345164 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345164 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345164
Register mapping to map architectural registers to corresponding physical registers based on a mode indicating a register length Jun 29, 2023 Issued
Array ( [id] => 18904639 [patent_doc_number] => 20240020124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => Supporting Multiple Vector Lengths with Configurable Vector Register File [patent_app_type] => utility [patent_app_number] => 18/345007 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345007 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345007
Supporting Multiple Vector Lengths with Configurable Vector Register File Jun 29, 2023 Pending
Array ( [id] => 19686217 [patent_doc_number] => 20250004762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => BINARY CONVOLUTION INSTRUCTIONS FOR BINARY NEURAL NETWORK COMPUTATIONS [patent_app_type] => utility [patent_app_number] => 18/344091 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344091
BINARY CONVOLUTION INSTRUCTIONS FOR BINARY NEURAL NETWORK COMPUTATIONS Jun 28, 2023 Pending
Array ( [id] => 19686231 [patent_doc_number] => 20250004776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => INSTRUCTION FLOW REGULATOR FOR A PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 18/216201 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18216201 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/216201
INSTRUCTION FLOW REGULATOR FOR A PROCESSING UNIT Jun 28, 2023 Pending
Array ( [id] => 19660662 [patent_doc_number] => 20240427727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => HANDLING DYNAMIC TENSOR LENGTHS IN A RECONFIGURABLE PROCESSOR THAT INCLUDES MULTIPLE MEMORY UNITS [patent_app_type] => utility [patent_app_number] => 18/213598 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18213598 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/213598
HANDLING DYNAMIC TENSOR LENGTHS IN A RECONFIGURABLE PROCESSOR THAT INCLUDES MULTIPLE MEMORY UNITS Jun 22, 2023 Pending
Array ( [id] => 18819511 [patent_doc_number] => 20230393851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => PROCESSING SYSTEM WITH INTEGRATED DOMAIN SPECIFIC ACCELERATORS [patent_app_type] => utility [patent_app_number] => 18/212128 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18212128 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/212128
PROCESSING SYSTEM WITH INTEGRATED DOMAIN SPECIFIC ACCELERATORS Jun 19, 2023 Pending
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