Clare E. Heflin

Array ( [id] => 13707331 [patent_doc_number] => 20170364620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => Verification of Untimed Nets [patent_app_type] => utility [patent_app_number] => 15/182655 [patent_app_country] => US [patent_app_date] => 2016-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15182655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11352675 [patent_doc_number] => 20160371415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'SYSTEM AND METHOD FOR DESIGNING POWER SYSTEMS' [patent_app_type] => utility [patent_app_number] => 15/182767 [patent_app_country] => US [patent_app_date] => 2016-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6098 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15182767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13707337 [patent_doc_number] => 20170364623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => DESIGN/TECHNOLOGY CO-OPTIMIZATION PLATFORM FOR HIGH-MOBILITY CHANNELS CMOS TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 15/183333 [patent_app_country] => US [patent_app_date] => 2016-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4630 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15183333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13693579 [patent_doc_number] => 20170357744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => GLOBAL ROUTING FRAMEWORK OF INTEGRATED CIRCUIT BASED ON LOCALIZED ROUTING OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 15/181970 [patent_app_country] => US [patent_app_date] => 2016-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15181970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14150039 [patent_doc_number] => 10255401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Viewing multi paired schematic and layout windows on printed circuit board (PCB) design software and tools [patent_app_type] => utility [patent_app_number] => 15/167864 [patent_app_country] => US [patent_app_date] => 2016-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5572 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15167864 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11271919 [patent_doc_number] => 20160334467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'METHOD AND APPARATUS FOR INJECTING FAULT AND ANALYZING FAULT TOLERANCE' [patent_app_type] => utility [patent_app_number] => 15/154829 [patent_app_country] => US [patent_app_date] => 2016-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15154829 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12047359 [patent_doc_number] => 09824968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Method, system and computer readable medium using stitching for mask assignment of patterns' [patent_app_type] => utility [patent_app_number] => 15/139615 [patent_app_country] => US [patent_app_date] => 2016-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 8209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15139615 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14201489 [patent_doc_number] => 10267853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => System and method to diagnose integrated circuit [patent_app_type] => utility [patent_app_number] => 15/137833 [patent_app_country] => US [patent_app_date] => 2016-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15137833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12249373 [patent_doc_number] => 09922149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Integration of functional analysis and common path pessimism removal in static timing analysis' [patent_app_type] => utility [patent_app_number] => 15/132554 [patent_app_country] => US [patent_app_date] => 2016-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5332 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15132554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16966577 [patent_doc_number] => 20210218076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => METHOD AND DEVICE FOR USING AN ELECTROCHEMICAL ENERGY STORE SO AS TO OPTIMIZE THE SERVICE LIFE [patent_app_type] => utility [patent_app_number] => 16/093241 [patent_app_country] => US [patent_app_date] => 2016-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16093241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11036760 [patent_doc_number] => 20160233716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'METHOD FOR PERFORMING WIRELESS CHARGING CONTROL OF AN ELECTRONIC DEVICE WITH AID OF SIMPLE RESPONSE INDICATING ACKNOWLEDGEMENT, AND ASSOCIATED APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/098338 [patent_app_country] => US [patent_app_date] => 2016-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 20630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15098338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12196105 [patent_doc_number] => 09899848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Mobile terminal, DC-charging power source adaptor, and charging method' [patent_app_type] => utility [patent_app_number] => 15/064010 [patent_app_country] => US [patent_app_date] => 2016-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11131 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15064010 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12148143 [patent_doc_number] => 09882408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-30 [patent_title] => 'Battery charging system including current observer circuitry to avoid battery voltage overshoot based on battery current draw' [patent_app_type] => utility [patent_app_number] => 15/053750 [patent_app_country] => US [patent_app_date] => 2016-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4829 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15053750 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11056486 [patent_doc_number] => 20160253449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'THREE DIMENSIONAL (3D) VIRTUAL IMAGE MODELING METHOD FOR OBJECT PRODUCED THROUGH SEMICONDUCTOR MANUFACTURING PROCESS' [patent_app_type] => utility [patent_app_number] => 15/052372 [patent_app_country] => US [patent_app_date] => 2016-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3062 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15052372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14705083 [patent_doc_number] => 10380291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => System and method for high-speed serial link design [patent_app_type] => utility [patent_app_number] => 15/050582 [patent_app_country] => US [patent_app_date] => 2016-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 31 [patent_no_of_words] => 5876 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15050582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11938804 [patent_doc_number] => 20170242954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'LAYOUT CHECKING SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 15/051473 [patent_app_country] => US [patent_app_date] => 2016-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8986 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15051473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11938795 [patent_doc_number] => 20170242945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'DISTRIBUTED TIMING ANALYSIS OF A PARTITIONED INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 15/049501 [patent_app_country] => US [patent_app_date] => 2016-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15049501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11938803 [patent_doc_number] => 20170242953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'Preserving Hierarchy And Coloring Uniformity In Multi-Patterning Layout Design' [patent_app_type] => utility [patent_app_number] => 15/050447 [patent_app_country] => US [patent_app_date] => 2016-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9362 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15050447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11501846 [patent_doc_number] => 20170076031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'METHOD, APPARATUS AND SYSTEM FOR USING HYBRID LIBRARY TRACK DESIGN FOR SOI TECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 15/047878 [patent_app_country] => US [patent_app_date] => 2016-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15047878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10826725 [patent_doc_number] => 20160172895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'WIRELESS POWER TRANSFER METHOD, APPARATUS AND SYSTEM FOR LOW AND MEDIUM POWER' [patent_app_type] => utility [patent_app_number] => 15/018946 [patent_app_country] => US [patent_app_date] => 2016-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 17273 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15018946 [rel_patent_id] =>[rel_patent_doc_number] =>)