Search

Clare E. Heflin

Examiner (ID: 11131, Phone: (571)272-2604 , Office: P/2911 )

Most Active Art Unit
2911
Art Unit(s)
2911
Total Applications
5735
Issued Applications
5670
Pending Applications
1
Abandoned Applications
64

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11452282 [patent_doc_number] => 09575929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Apparatus of wave-pipelined circuits' [patent_app_type] => utility [patent_app_number] => 15/017551 [patent_app_country] => US [patent_app_date] => 2016-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 27 [patent_no_of_words] => 19355 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15017551 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/017551
Apparatus of wave-pipelined circuits Feb 4, 2016 Issued
Array ( [id] => 13651857 [patent_doc_number] => 09852244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-26 [patent_title] => Efficient waveform generation for emulation [patent_app_type] => utility [patent_app_number] => 15/007040 [patent_app_country] => US [patent_app_date] => 2016-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15007040 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/007040
Efficient waveform generation for emulation Jan 25, 2016 Issued
Array ( [id] => 15232253 [patent_doc_number] => 10503851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => CMOS-photonics co-design [patent_app_type] => utility [patent_app_number] => 16/065716 [patent_app_country] => US [patent_app_date] => 2016-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3723 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16065716 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/065716
CMOS-photonics co-design Jan 21, 2016 Issued
Array ( [id] => 11027755 [patent_doc_number] => 20160224711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'DISTRIBUTED LC RESONANT TANKS CLOCK TREE SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 14/994999 [patent_app_country] => US [patent_app_date] => 2016-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3031 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14994999 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/994999
Distributed LC resonant tanks clock tree synthesis Jan 12, 2016 Issued
Array ( [id] => 12433992 [patent_doc_number] => 09977845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-22 [patent_title] => Method of performing static timing analysis for an integrated circuit [patent_app_type] => utility [patent_app_number] => 14/982921 [patent_app_country] => US [patent_app_date] => 2015-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 8891 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14982921 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/982921
Method of performing static timing analysis for an integrated circuit Dec 28, 2015 Issued
Array ( [id] => 10752355 [patent_doc_number] => 20160098507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'INTEGRATED CIRCUIT DEVICE CONFIGURATION METHODS ADAPTED TO ACCOUNT FOR RETIMING' [patent_app_type] => utility [patent_app_number] => 14/966229 [patent_app_country] => US [patent_app_date] => 2015-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5152 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14966229 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/966229
Integrated circuit device configuration methods adapted to account for retiming Dec 10, 2015 Issued
Array ( [id] => 14643185 [patent_doc_number] => 10366339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Method for efficient implementation of diagonal operators over clifford+T basis [patent_app_type] => utility [patent_app_number] => 15/528086 [patent_app_country] => US [patent_app_date] => 2015-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6642 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15528086 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/528086
Method for efficient implementation of diagonal operators over clifford+T basis Nov 19, 2015 Issued
Array ( [id] => 10732013 [patent_doc_number] => 20160078163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'MANAGEMENT APPARATUS, SUBSTRATE PROCESSING SYSTEM AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 14/946965 [patent_app_country] => US [patent_app_date] => 2015-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13089 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14946965 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/946965
Management apparatus, substrate processing system and non-transitory computer-readable recording medium Nov 19, 2015 Issued
Array ( [id] => 10801477 [patent_doc_number] => 20160147634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'METHOD AND APPARATUS FOR OBTAINING CONSTRAINTS ON EVENTS' [patent_app_type] => utility [patent_app_number] => 14/946815 [patent_app_country] => US [patent_app_date] => 2015-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9122 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14946815 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/946815
METHOD AND APPARATUS FOR OBTAINING CONSTRAINTS ON EVENTS Nov 19, 2015 Abandoned
Array ( [id] => 11910381 [patent_doc_number] => 09779194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Link system, link program, and link method' [patent_app_type] => utility [patent_app_number] => 14/946900 [patent_app_country] => US [patent_app_date] => 2015-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 29 [patent_no_of_words] => 13948 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14946900 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/946900
Link system, link program, and link method Nov 19, 2015 Issued
Array ( [id] => 11186797 [patent_doc_number] => 09418201 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-16 [patent_title] => 'Integration of functional analysis and common path pessimism removal in static timing analysis' [patent_app_type] => utility [patent_app_number] => 14/945928 [patent_app_country] => US [patent_app_date] => 2015-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5298 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14945928 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/945928
Integration of functional analysis and common path pessimism removal in static timing analysis Nov 18, 2015 Issued
Array ( [id] => 12256186 [patent_doc_number] => 09928332 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-27 [patent_title] => 'Systems and methods for time-multiplexed synchronous logic' [patent_app_type] => utility [patent_app_number] => 14/946227 [patent_app_country] => US [patent_app_date] => 2015-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 5228 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14946227 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/946227
Systems and methods for time-multiplexed synchronous logic Nov 18, 2015 Issued
Array ( [id] => 11897303 [patent_doc_number] => 09767240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'Temperature-aware integrated circuit design methods and systems' [patent_app_type] => utility [patent_app_number] => 14/945530 [patent_app_country] => US [patent_app_date] => 2015-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 12084 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14945530 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/945530
Temperature-aware integrated circuit design methods and systems Nov 18, 2015 Issued
Array ( [id] => 14490083 [patent_doc_number] => 10331832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Floating node reduction using random walk method [patent_app_type] => utility [patent_app_number] => 14/946197 [patent_app_country] => US [patent_app_date] => 2015-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7378 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14946197 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/946197
Floating node reduction using random walk method Nov 18, 2015 Issued
Array ( [id] => 11552307 [patent_doc_number] => 09621173 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-11 [patent_title] => 'Circuits and methods of implementing time-average-frequency direct period synthesizer on programmable logic chip and driving applications using the same' [patent_app_type] => utility [patent_app_number] => 14/945468 [patent_app_country] => US [patent_app_date] => 2015-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6198 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14945468 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/945468
Circuits and methods of implementing time-average-frequency direct period synthesizer on programmable logic chip and driving applications using the same Nov 18, 2015 Issued
Array ( [id] => 11651835 [patent_doc_number] => 20170147736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'AUTOMATED SCAN CHAIN DIAGNOSTICS USING EMISSION' [patent_app_type] => utility [patent_app_number] => 14/945892 [patent_app_country] => US [patent_app_date] => 2015-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4815 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14945892 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/945892
Automated scan chain diagnostics using emission Nov 18, 2015 Issued
Array ( [id] => 10740675 [patent_doc_number] => 20160086825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF ADAPTIVE PATTERNING FOR PANELIZED PACKAGING' [patent_app_type] => utility [patent_app_number] => 14/944059 [patent_app_country] => US [patent_app_date] => 2015-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 22216 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14944059 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/944059
Semiconductor device and method of adaptive patterning for panelized packaging Nov 16, 2015 Issued
Array ( [id] => 12089483 [patent_doc_number] => 09843221 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-12 [patent_title] => 'Redundant charging and discharging MOSFET driving in battery backup system' [patent_app_type] => utility [patent_app_number] => 14/933421 [patent_app_country] => US [patent_app_date] => 2015-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14933421 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/933421
Redundant charging and discharging MOSFET driving in battery backup system Nov 4, 2015 Issued
Array ( [id] => 11516587 [patent_doc_number] => 20170083661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'INTEGRATED CIRCUIT CHIP DESIGN METHODS AND SYSTEMS USING PROCESS WINDOW-AWARE TIMING ANALYSIS' [patent_app_type] => utility [patent_app_number] => 14/862652 [patent_app_country] => US [patent_app_date] => 2015-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862652 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/862652
Integrated circuit chip design methods and systems using process window-aware timing analysis Sep 22, 2015 Issued
Array ( [id] => 11326236 [patent_doc_number] => 20160356848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'APPARATUS AND METHOD OF GENERATING TEST PATTERN, TEST SYSTEM USING THE SAME, AND COMPUTER PROGRAM THEREFOR' [patent_app_type] => utility [patent_app_number] => 14/862386 [patent_app_country] => US [patent_app_date] => 2015-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4442 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862386 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/862386
Apparatus and method of generating test pattern, test system using the same, and computer program therefor Sep 22, 2015 Issued
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