Search

Clare E. Heflin

Examiner (ID: 11131, Phone: (571)272-2604 , Office: P/2911 )

Most Active Art Unit
2911
Art Unit(s)
2911
Total Applications
5735
Issued Applications
5670
Pending Applications
1
Abandoned Applications
64

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9861953 [patent_doc_number] => 20150041970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/523062 [patent_app_country] => US [patent_app_date] => 2014-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4948 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14523062 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/523062
Semiconductor device with layout of wiring layer and dummy patterns Oct 23, 2014 Issued
Array ( [id] => 11509223 [patent_doc_number] => 09600384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'System-on-chip verification' [patent_app_type] => utility [patent_app_number] => 14/513361 [patent_app_country] => US [patent_app_date] => 2014-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5369 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14513361 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/513361
System-on-chip verification Oct 13, 2014 Issued
Array ( [id] => 11193570 [patent_doc_number] => 09424385 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-23 [patent_title] => 'SRAM cell layout structure and devices therefrom' [patent_app_type] => utility [patent_app_number] => 14/511487 [patent_app_country] => US [patent_app_date] => 2014-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11990 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14511487 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/511487
SRAM cell layout structure and devices therefrom Oct 9, 2014 Issued
Array ( [id] => 10747452 [patent_doc_number] => 20160093603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'SYSTEM AND METHOD OF PROCESSING CUTTING LAYOUT AND EXAMPLE SWITCHING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/500528 [patent_app_country] => US [patent_app_date] => 2014-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9915 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14500528 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/500528
System and method of processing cutting layout and example switching circuit Sep 28, 2014 Issued
Array ( [id] => 11024506 [patent_doc_number] => 20160221462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'SYSTEM AND METHOD FOR CHARGING A TRACTION BATTERY LIMITING THE CURRENT DRAW OF PARASITIC CAPACITANCES' [patent_app_type] => utility [patent_app_number] => 14/917466 [patent_app_country] => US [patent_app_date] => 2014-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5246 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14917466 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/917466
SYSTEM AND METHOD FOR CHARGING A TRACTION BATTERY LIMITING THE CURRENT DRAW OF PARASITIC CAPACITANCES Sep 23, 2014 Abandoned
Array ( [id] => 10264976 [patent_doc_number] => 20150149973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'THIRD PARTY COMPONENT DEBUGGING FOR INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 14/491834 [patent_app_country] => US [patent_app_date] => 2014-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5309 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14491834 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/491834
Third party component debugging for integrated circuit design Sep 18, 2014 Issued
Array ( [id] => 9795179 [patent_doc_number] => 20150007123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'SYSTEMS AND METHODS FOR DESIGNING AND MAKING INTEGRATED CIRCUITS WITH CONSIDERATION OF WIRING DEMAND RATION' [patent_app_type] => utility [patent_app_number] => 14/486723 [patent_app_country] => US [patent_app_date] => 2014-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11553 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14486723 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/486723
Systems and methods for designing integrated circuits with consideration of horizontal and vertical wiring demand ratios Sep 14, 2014 Issued
Array ( [id] => 9841116 [patent_doc_number] => 20150033198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-29 [patent_title] => 'INTEGRATED CIRCUIT DEVICE CONFIGURATION METHODS ADAPTED TO ACCOUNT FOR RETIMING' [patent_app_type] => utility [patent_app_number] => 14/484655 [patent_app_country] => US [patent_app_date] => 2014-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5155 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14484655 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/484655
Integrated circuit device configuration methods adapted to account for retiming Sep 11, 2014 Issued
Array ( [id] => 11027751 [patent_doc_number] => 20160224708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'METHOD FOR ANALYZING THE BEHAVIOR OF AN INTEGRATED CIRCUIT IMPLEMENTED BY COMPUTER' [patent_app_type] => utility [patent_app_number] => 14/914622 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6256 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14914622 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/914622
Method for analyzing the behavior of an integrated circuit implemented by computer Sep 2, 2014 Issued
Array ( [id] => 13172411 [patent_doc_number] => 10102322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Computer implemented method for behavior analysis of an integrated circuit comprising paths selection based on an aggregation criterion and predefined analysis strategy [patent_app_type] => utility [patent_app_number] => 14/914621 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14914621 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/914621
Computer implemented method for behavior analysis of an integrated circuit comprising paths selection based on an aggregation criterion and predefined analysis strategy Sep 2, 2014 Issued
Array ( [id] => 14825867 [patent_doc_number] => 10409943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Efficient analog layout prototyping by layout reuse with routing preservation [patent_app_type] => utility [patent_app_number] => 14/475276 [patent_app_country] => US [patent_app_date] => 2014-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 42 [patent_no_of_words] => 14512 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475276 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/475276
Efficient analog layout prototyping by layout reuse with routing preservation Sep 1, 2014 Issued
Array ( [id] => 11860411 [patent_doc_number] => 09740092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Model-based generation of dummy features' [patent_app_type] => utility [patent_app_number] => 14/467489 [patent_app_country] => US [patent_app_date] => 2014-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5537 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14467489 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/467489
Model-based generation of dummy features Aug 24, 2014 Issued
Array ( [id] => 10252763 [patent_doc_number] => 20150137759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'Automated Mobile Device Battery Charging Kiosks' [patent_app_type] => utility [patent_app_number] => 14/466761 [patent_app_country] => US [patent_app_date] => 2014-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5181 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14466761 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/466761
Automated Mobile Device Battery Charging Kiosks Aug 21, 2014 Abandoned
Array ( [id] => 10710511 [patent_doc_number] => 20160056658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'SMART WIRELESS CHARGER' [patent_app_type] => utility [patent_app_number] => 14/466030 [patent_app_country] => US [patent_app_date] => 2014-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1564 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14466030 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/466030
Smart wireless charger Aug 21, 2014 Issued
Array ( [id] => 10371015 [patent_doc_number] => 20150256021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'COVER MEMBER, ELECTRONIC DEVICE, AND METHOD FOR WIRELESS CHARGING' [patent_app_type] => utility [patent_app_number] => 14/466252 [patent_app_country] => US [patent_app_date] => 2014-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10716 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14466252 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/466252
Cover member, electronic device, and method for wireless charging Aug 21, 2014 Issued
Array ( [id] => 10706262 [patent_doc_number] => 20160052409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'OFF-BOARD CHARGER FOR HIGH-VOLTAGE BATTERY CHARGING' [patent_app_type] => utility [patent_app_number] => 14/466175 [patent_app_country] => US [patent_app_date] => 2014-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4243 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14466175 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/466175
Off-board charger for high-voltage battery charging Aug 21, 2014 Issued
Array ( [id] => 10637700 [patent_doc_number] => 09355204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-31 [patent_title] => 'Method of decomposing design layout for double patterning process' [patent_app_type] => utility [patent_app_number] => 14/463851 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 5283 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14463851 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/463851
Method of decomposing design layout for double patterning process Aug 19, 2014 Issued
Array ( [id] => 11258693 [patent_doc_number] => 09483593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Method for decomposing a hardware model and for accelerating formal verification of the hardware model' [patent_app_type] => utility [patent_app_number] => 14/463857 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 10565 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14463857 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/463857
Method for decomposing a hardware model and for accelerating formal verification of the hardware model Aug 19, 2014 Issued
Array ( [id] => 11452447 [patent_doc_number] => 09576094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Logic circuit and system and computer program product for logic synthesis' [patent_app_type] => utility [patent_app_number] => 14/464366 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12531 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464366 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/464366
Logic circuit and system and computer program product for logic synthesis Aug 19, 2014 Issued
Array ( [id] => 11860425 [patent_doc_number] => 09740108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Scatterometry overlay metrology targets and methods' [patent_app_type] => utility [patent_app_number] => 14/457780 [patent_app_country] => US [patent_app_date] => 2014-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5017 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14457780 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/457780
Scatterometry overlay metrology targets and methods Aug 11, 2014 Issued
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