Clayton E. Laballe

Array ( [id] => 3544184 [patent_doc_number] => 05584003 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Control systems having an address conversion device for controlling a cache memory and a cache tag memory' [patent_app_type] => 1 [patent_app_number] => 8/575265 [patent_app_country] => US [patent_app_date] => 1995-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6323 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/584/05584003.pdf [firstpage_image] =>[orig_patent_app_number] => 575265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3603748 [patent_doc_number] => 05586298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Effective use of memory bus in a multiprocessing environment by controlling end of data intervention by a snooping cache' [patent_app_type] => 1 [patent_app_number] => 8/467896 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3438 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586298.pdf [firstpage_image] =>[orig_patent_app_number] => 467896 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3621367 [patent_doc_number] => 05590310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Method and structure for data integrity in a multiple level cache system' [patent_app_type] => 1 [patent_app_number] => 8/426440 [patent_app_country] => US [patent_app_date] => 1995-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4366 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590310.pdf [firstpage_image] =>[orig_patent_app_number] => 426440 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3575961 [patent_doc_number] => 05526513 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-11 [patent_title] => 'Memory addressing device' [patent_app_type] => 1 [patent_app_number] => 8/344634 [patent_app_country] => US [patent_app_date] => 1994-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4179 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 384 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/526/05526513.pdf [firstpage_image] =>[orig_patent_app_number] => 344634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3612385 [patent_doc_number] => 05559990 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Memories with burst mode access' [patent_app_type] => 1 [patent_app_number] => 8/328337 [patent_app_country] => US [patent_app_date] => 1994-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 7489 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559990.pdf [firstpage_image] =>[orig_patent_app_number] => 328337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3567013 [patent_doc_number] => 05500948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-19 [patent_title] => 'Translating instruction pointer virtual addresses to physical addresses for accessing an instruction cache' [patent_app_type] => 1 [patent_app_number] => 8/274214 [patent_app_country] => US [patent_app_date] => 1994-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4048 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/500/05500948.pdf [firstpage_image] =>[orig_patent_app_number] => 274214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3128685 [patent_doc_number] => 05410665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Process controller single memory chip shadowing technique' [patent_app_type] => 1 [patent_app_number] => 8/259087 [patent_app_country] => US [patent_app_date] => 1994-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2572 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/410/05410665.pdf [firstpage_image] =>[orig_patent_app_number] => 259087 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3549083 [patent_doc_number] => 05495593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Microcontroller device having remotely programmable EPROM and method for programming' [patent_app_type] => 1 [patent_app_number] => 8/254656 [patent_app_country] => US [patent_app_date] => 1994-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5926 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/495/05495593.pdf [firstpage_image] =>[orig_patent_app_number] => 254656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3530431 [patent_doc_number] => 05577226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Method and system for coherently caching I/O devices across a network' [patent_app_type] => 1 [patent_app_number] => 8/238815 [patent_app_country] => US [patent_app_date] => 1994-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 16116 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/577/05577226.pdf [firstpage_image] =>[orig_patent_app_number] => 238815 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3437822 [patent_doc_number] => 05404478 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Method of managing a virtual storage for a multi-processor system' [patent_app_type] => 1 [patent_app_number] => 8/227499 [patent_app_country] => US [patent_app_date] => 1994-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 8822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404478.pdf [firstpage_image] =>[orig_patent_app_number] => 227499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3532289 [patent_doc_number] => 05530837 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Methods and apparatus for interleaving memory transactions into an arbitrary number of banks' [patent_app_type] => 1 [patent_app_number] => 8/218715 [patent_app_country] => US [patent_app_date] => 1994-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6388 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530837.pdf [firstpage_image] =>[orig_patent_app_number] => 218715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3138571 [patent_doc_number] => 05437019 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-25 [patent_title] => 'Addressing method and apparatus for a computer system' [patent_app_type] => 1 [patent_app_number] => 8/217001 [patent_app_country] => US [patent_app_date] => 1994-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5744 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/437/05437019.pdf [firstpage_image] =>[orig_patent_app_number] => 217001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3626843 [patent_doc_number] => 05511206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Microprocessor based computer with virtual memory space in overwritable memory' [patent_app_type] => 1 [patent_app_number] => 8/202696 [patent_app_country] => US [patent_app_date] => 1994-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3727 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/511/05511206.pdf [firstpage_image] =>[orig_patent_app_number] => 202696 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3500934 [patent_doc_number] => 05471560 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Method of construction of hierarchically organized procedural node information structure including a method for extracting procedural knowledge from an expert, and procedural node information structure constructed thereby' [patent_app_type] => 1 [patent_app_number] => 8/197661 [patent_app_country] => US [patent_app_date] => 1994-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6106 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 444 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471560.pdf [firstpage_image] =>[orig_patent_app_number] => 197661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3440924 [patent_doc_number] => 05463757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Command interface between user commands and a memory device' [patent_app_type] => 1 [patent_app_number] => 8/185449 [patent_app_country] => US [patent_app_date] => 1994-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7915 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463757.pdf [firstpage_image] =>[orig_patent_app_number] => 185449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3540205 [patent_doc_number] => 05542066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Destaging modified data blocks from cache memory' [patent_app_type] => 1 [patent_app_number] => 8/172527 [patent_app_country] => US [patent_app_date] => 1993-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12329 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/542/05542066.pdf [firstpage_image] =>[orig_patent_app_number] => 172527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3531717 [patent_doc_number] => 05530799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Rendering cache in an object oriented system' [patent_app_type] => 1 [patent_app_number] => 8/169862 [patent_app_country] => US [patent_app_date] => 1993-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5916 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530799.pdf [firstpage_image] =>[orig_patent_app_number] => 169862 [rel_patent_id] =>[rel_patent_doc_number] =>)