Search

Clayton E. Laballe

Examiner (ID: 13914)

Most Active Art Unit
2102
Art Unit(s)
2862, 3621, 2102, 2834, 2852, 1106
Total Applications
921
Issued Applications
755
Pending Applications
35
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3604603 [patent_doc_number] => 05568632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Method and apparatus for cache memory' [patent_app_type] => 1 [patent_app_number] => 8/169572 [patent_app_country] => US [patent_app_date] => 1993-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6389 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568632.pdf [firstpage_image] =>[orig_patent_app_number] => 169572 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/169572
Method and apparatus for cache memory Dec 16, 1993 Issued
Array ( [id] => 3532179 [patent_doc_number] => 05530830 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Disk array system' [patent_app_type] => 1 [patent_app_number] => 8/163022 [patent_app_country] => US [patent_app_date] => 1993-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4671 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530830.pdf [firstpage_image] =>[orig_patent_app_number] => 163022 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/163022
Disk array system Dec 5, 1993 Issued
Array ( [id] => 3497450 [patent_doc_number] => 05426751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Information processing apparatus with address extension function' [patent_app_type] => 1 [patent_app_number] => 8/153612 [patent_app_country] => US [patent_app_date] => 1993-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3632 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426751.pdf [firstpage_image] =>[orig_patent_app_number] => 153612 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/153612
Information processing apparatus with address extension function Nov 16, 1993 Issued
Array ( [id] => 3427042 [patent_doc_number] => 05454092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-26 [patent_title] => 'Microcomputer having an improved internal address mapping apparatus' [patent_app_type] => 1 [patent_app_number] => 8/151719 [patent_app_country] => US [patent_app_date] => 1993-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3993 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/454/05454092.pdf [firstpage_image] =>[orig_patent_app_number] => 151719 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/151719
Microcomputer having an improved internal address mapping apparatus Nov 14, 1993 Issued
08/152264 ARCHITECTURE AND CONFIGURING METHOD FOR A COMPUTER EXPANSION BOARD Nov 11, 1993 Abandoned
Array ( [id] => 3066350 [patent_doc_number] => 05351189 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-27 [patent_title] => 'Machine translation system including separated side-by-side display of original and corresponding translated sentences' [patent_app_type] => 1 [patent_app_number] => 8/130416 [patent_app_country] => US [patent_app_date] => 1993-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3711 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/351/05351189.pdf [firstpage_image] =>[orig_patent_app_number] => 130416 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/130416
Machine translation system including separated side-by-side display of original and corresponding translated sentences Sep 30, 1993 Issued
Array ( [id] => 3626950 [patent_doc_number] => 05535399 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Solid state disk drive unit having on-board backup non-volatile memory' [patent_app_type] => 1 [patent_app_number] => 8/130047 [patent_app_country] => US [patent_app_date] => 1993-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 42 [patent_no_of_words] => 12280 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535399.pdf [firstpage_image] =>[orig_patent_app_number] => 130047 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/130047
Solid state disk drive unit having on-board backup non-volatile memory Sep 29, 1993 Issued
08/100100 MULTIPROCESSOR DIGITAL DATA PROCESSING SYSTEM Jul 29, 1993 Pending
Array ( [id] => 3035217 [patent_doc_number] => 05327542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-05 [patent_title] => 'Data processor implementing a two\'s complement addressing technique' [patent_app_type] => 1 [patent_app_number] => 8/089383 [patent_app_country] => US [patent_app_date] => 1993-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2814 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/327/05327542.pdf [firstpage_image] =>[orig_patent_app_number] => 089383 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/089383
Data processor implementing a two's complement addressing technique Jul 7, 1993 Issued
Array ( [id] => 3439087 [patent_doc_number] => 05404560 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Microprocessor having external control store' [patent_app_type] => 1 [patent_app_number] => 8/083852 [patent_app_country] => US [patent_app_date] => 1993-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 17165 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404560.pdf [firstpage_image] =>[orig_patent_app_number] => 083852 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/083852
Microprocessor having external control store Jun 24, 1993 Issued
Array ( [id] => 3420118 [patent_doc_number] => 05438670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-01 [patent_title] => 'Method of prechecking the validity of a write access request' [patent_app_type] => 1 [patent_app_number] => 8/084316 [patent_app_country] => US [patent_app_date] => 1993-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 21111 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 472 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/438/05438670.pdf [firstpage_image] =>[orig_patent_app_number] => 084316 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/084316
Method of prechecking the validity of a write access request Jun 24, 1993 Issued
Array ( [id] => 3561324 [patent_doc_number] => 05546560 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Device and method for reducing bus activity in a computer system having multiple bus-masters' [patent_app_type] => 1 [patent_app_number] => 8/081080 [patent_app_country] => US [patent_app_date] => 1993-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3747 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546560.pdf [firstpage_image] =>[orig_patent_app_number] => 081080 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/081080
Device and method for reducing bus activity in a computer system having multiple bus-masters Jun 21, 1993 Issued
Array ( [id] => 3472082 [patent_doc_number] => 05442770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'Triple port cache memory' [patent_app_type] => 1 [patent_app_number] => 8/076286 [patent_app_country] => US [patent_app_date] => 1993-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2011 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/442/05442770.pdf [firstpage_image] =>[orig_patent_app_number] => 076286 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/076286
Triple port cache memory Jun 10, 1993 Issued
Array ( [id] => 3505663 [patent_doc_number] => 05537573 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Cache system and method for prefetching of data' [patent_app_type] => 1 [patent_app_number] => 8/069147 [patent_app_country] => US [patent_app_date] => 1993-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 6510 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537573.pdf [firstpage_image] =>[orig_patent_app_number] => 069147 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/069147
Cache system and method for prefetching of data May 27, 1993 Issued
Array ( [id] => 3565917 [patent_doc_number] => 05574868 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Bus grant prediction technique for a split transaction bus in a multiprocessor computer system' [patent_app_type] => 1 [patent_app_number] => 8/062065 [patent_app_country] => US [patent_app_date] => 1993-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1867 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574868.pdf [firstpage_image] =>[orig_patent_app_number] => 062065 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/062065
Bus grant prediction technique for a split transaction bus in a multiprocessor computer system May 13, 1993 Issued
08/056737 MICROCONTROLLER DEVICE HAVING REMOTELY PROGRAMMABLE EPROM AND METHOD FOR PROGRAMMING Apr 27, 1993 Pending
Array ( [id] => 3497607 [patent_doc_number] => 05426762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'System for determining a truth of software in an information processing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/043745 [patent_app_country] => US [patent_app_date] => 1993-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5915 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426762.pdf [firstpage_image] =>[orig_patent_app_number] => 043745 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/043745
System for determining a truth of software in an information processing apparatus Apr 6, 1993 Issued
Array ( [id] => 3502730 [patent_doc_number] => 05440715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Method and apparatus for expanding the width of a content addressable memory using a continuation bit' [patent_app_type] => 1 [patent_app_number] => 8/044543 [patent_app_country] => US [patent_app_date] => 1993-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7936 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440715.pdf [firstpage_image] =>[orig_patent_app_number] => 044543 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/044543
Method and apparatus for expanding the width of a content addressable memory using a continuation bit Apr 5, 1993 Issued
08/042835 METHOD FOR PROTECTING CIRCUIT CONFIGURATIONS HAVING AN ELECTRICALLY PROGRAMMABLE NON-VOLATILE MEMORY USED AS A COUNTER FROM BOUNDARY-VALUE AMBIGUOUS PROGRAMMING OF THE MEMORY AND A CIRCUIT CONFIGURATION FOR PERFORMING THE METHOD Apr 4, 1993 Pending
Array ( [id] => 3128757 [patent_doc_number] => 05410669 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Data processor having a cache memory capable of being used as a linear ram bank' [patent_app_type] => 1 [patent_app_number] => 8/043065 [patent_app_country] => US [patent_app_date] => 1993-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2761 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/410/05410669.pdf [firstpage_image] =>[orig_patent_app_number] => 043065 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/043065
Data processor having a cache memory capable of being used as a linear ram bank Apr 4, 1993 Issued
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