Search

Clayton E. Laballe

Examiner (ID: 13914)

Most Active Art Unit
2102
Art Unit(s)
2862, 3621, 2102, 2834, 2852, 1106
Total Applications
921
Issued Applications
755
Pending Applications
35
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
07/650987 FILING SYSTEM WITH MULTIPLE FORMS OF STORAGE Feb 3, 1991 Abandoned
07/650133 MICROCOMPUTER HAVING AN IMPROVED INTERNAL MEMORY ADDRESS MAPPING APPARATUS Feb 3, 1991 Abandoned
Array ( [id] => 2963351 [patent_doc_number] => 05263140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-16 [patent_title] => 'Variable page size per entry translation look-aside buffer' [patent_app_type] => 1 [patent_app_number] => 7/644705 [patent_app_country] => US [patent_app_date] => 1991-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2815 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/263/05263140.pdf [firstpage_image] =>[orig_patent_app_number] => 644705 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/644705
Variable page size per entry translation look-aside buffer Jan 22, 1991 Issued
07/643130 MICROPROCESSOR BASED COMPUTER WITH VIRTUAL MEMORY SPACE IN OVERWRITABLE MEMORY Jan 17, 1991 Abandoned
Array ( [id] => 3023135 [patent_doc_number] => 05282275 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-25 [patent_title] => 'Address processor for a signal processor' [patent_app_type] => 1 [patent_app_number] => 7/639545 [patent_app_country] => US [patent_app_date] => 1991-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4560 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/282/05282275.pdf [firstpage_image] =>[orig_patent_app_number] => 639545 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/639545
Address processor for a signal processor Jan 9, 1991 Issued
Array ( [id] => 2958650 [patent_doc_number] => 05255379 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-19 [patent_title] => 'Method for automatically transitioning from V86 mode to protected mode in a computer system using an Intel 80386 or 80486 processor' [patent_app_type] => 1 [patent_app_number] => 7/636075 [patent_app_country] => US [patent_app_date] => 1990-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6861 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/255/05255379.pdf [firstpage_image] =>[orig_patent_app_number] => 636075 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/636075
Method for automatically transitioning from V86 mode to protected mode in a computer system using an Intel 80386 or 80486 processor Dec 27, 1990 Issued
07/630291 METHOD OF MANAGING A VIRTUAL STORAGE FOR A MULTI-PROCESSOR SYSTEM Dec 18, 1990 Abandoned
Array ( [id] => 3032664 [patent_doc_number] => 05303359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Arrangement for simultaneously translating logical page addresses to corresponding real ones in data processing system' [patent_app_type] => 1 [patent_app_number] => 7/631002 [patent_app_country] => US [patent_app_date] => 1990-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2482 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 414 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/303/05303359.pdf [firstpage_image] =>[orig_patent_app_number] => 631002 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/631002
Arrangement for simultaneously translating logical page addresses to corresponding real ones in data processing system Dec 18, 1990 Issued
07/628547 ADDRESSING METHOD AND APPARATUS FOR A COMPUTER SYSTEM Dec 16, 1990 Abandoned
Array ( [id] => 2866357 [patent_doc_number] => 05127103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-30 [patent_title] => 'Real-time tracing of dynamic local data in high level languages in the presence of process context switches' [patent_app_type] => 1 [patent_app_number] => 7/616723 [patent_app_country] => US [patent_app_date] => 1990-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 13159 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/127/05127103.pdf [firstpage_image] =>[orig_patent_app_number] => 616723 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/616723
Real-time tracing of dynamic local data in high level languages in the presence of process context switches Nov 15, 1990 Issued
Array ( [id] => 2980662 [patent_doc_number] => 05203000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'Power-up reset conditioned on direction of voltage change' [patent_app_type] => 1 [patent_app_number] => 7/617480 [patent_app_country] => US [patent_app_date] => 1990-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6497 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/203/05203000.pdf [firstpage_image] =>[orig_patent_app_number] => 617480 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/617480
Power-up reset conditioned on direction of voltage change Nov 14, 1990 Issued
07/603251 MEMORY CONTROLLER HAVING MEANS FOR COMPARING A DESIGNATED ADDRESS WITH ADDRESSES SETTING AN AREA IN A MEMORY Oct 24, 1990 Abandoned
07/601601 DATA PROCESSOR IMPLEMENTING A TWO'S COMPLEMENT ADDRESSING TECHNIQUE Oct 17, 1990 Abandoned
Array ( [id] => 2838455 [patent_doc_number] => 05117498 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-26 [patent_title] => 'Processer with flexible return from subroutine' [patent_app_type] => 1 [patent_app_number] => 7/586328 [patent_app_country] => US [patent_app_date] => 1990-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 11478 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/117/05117498.pdf [firstpage_image] =>[orig_patent_app_number] => 586328 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/586328
Processer with flexible return from subroutine Sep 18, 1990 Issued
Array ( [id] => 2934273 [patent_doc_number] => 05235691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-10 [patent_title] => 'Main memory initializing system' [patent_app_type] => 1 [patent_app_number] => 7/575960 [patent_app_country] => US [patent_app_date] => 1990-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4255 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/235/05235691.pdf [firstpage_image] =>[orig_patent_app_number] => 575960 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/575960
Main memory initializing system Aug 30, 1990 Issued
Array ( [id] => 3102837 [patent_doc_number] => 05278967 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'System for providing gapless data transfer from page-mode dynamic random access memories' [patent_app_type] => 1 [patent_app_number] => 7/576252 [patent_app_country] => US [patent_app_date] => 1990-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3809 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278967.pdf [firstpage_image] =>[orig_patent_app_number] => 576252 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/576252
System for providing gapless data transfer from page-mode dynamic random access memories Aug 30, 1990 Issued
Array ( [id] => 2976804 [patent_doc_number] => 05274782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Method and apparatus for dynamic detection and routing of non-uniform traffic in parallel buffered multistage interconnection networks' [patent_app_type] => 1 [patent_app_number] => 7/573610 [patent_app_country] => US [patent_app_date] => 1990-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 9436 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/274/05274782.pdf [firstpage_image] =>[orig_patent_app_number] => 573610 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/573610
Method and apparatus for dynamic detection and routing of non-uniform traffic in parallel buffered multistage interconnection networks Aug 26, 1990 Issued
Array ( [id] => 2951365 [patent_doc_number] => 05261069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-09 [patent_title] => 'Method of maintaining consistency of cached data in a database system' [patent_app_type] => 1 [patent_app_number] => 7/566732 [patent_app_country] => US [patent_app_date] => 1990-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6226 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/261/05261069.pdf [firstpage_image] =>[orig_patent_app_number] => 566732 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/566732
Method of maintaining consistency of cached data in a database system Aug 12, 1990 Issued
Array ( [id] => 2915525 [patent_doc_number] => 05249277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-28 [patent_title] => 'Optimized performance memory method and system' [patent_app_type] => 1 [patent_app_number] => 7/564431 [patent_app_country] => US [patent_app_date] => 1990-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 2239 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/249/05249277.pdf [firstpage_image] =>[orig_patent_app_number] => 564431 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/564431
Optimized performance memory method and system Aug 7, 1990 Issued
Array ( [id] => 2794106 [patent_doc_number] => 05093784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-03 [patent_title] => 'Data processor with efficient transfer between subroutines and main program' [patent_app_type] => 1 [patent_app_number] => 7/563806 [patent_app_country] => US [patent_app_date] => 1990-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5136 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 431 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/093/05093784.pdf [firstpage_image] =>[orig_patent_app_number] => 563806 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/563806
Data processor with efficient transfer between subroutines and main program Aug 5, 1990 Issued
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