Clayton E. Laballe

Array ( [id] => 3094900 [patent_doc_number] => 05280594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'Architecture for high speed contiguous sequential access memories' [patent_app_type] => 1 [patent_app_number] => 7/558033 [patent_app_country] => US [patent_app_date] => 1990-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2699 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/280/05280594.pdf [firstpage_image] =>[orig_patent_app_number] => 558033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2888238 [patent_doc_number] => 05119290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-02 [patent_title] => 'Alias address support' [patent_app_type] => 1 [patent_app_number] => 7/554186 [patent_app_country] => US [patent_app_date] => 1990-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 5458 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 456 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/119/05119290.pdf [firstpage_image] =>[orig_patent_app_number] => 554186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2947927 [patent_doc_number] => 05247630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'M-dimensional computer memory with m-1 dimensional hyperplane access' [patent_app_type] => 1 [patent_app_number] => 7/551103 [patent_app_country] => US [patent_app_date] => 1990-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2487 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/247/05247630.pdf [firstpage_image] =>[orig_patent_app_number] => 551103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2831340 [patent_doc_number] => 05095422 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-10 [patent_title] => 'Information transferring method and apparatus for transferring information from one memory area to another memory area' [patent_app_type] => 1 [patent_app_number] => 7/547410 [patent_app_country] => US [patent_app_date] => 1990-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3352 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/095/05095422.pdf [firstpage_image] =>[orig_patent_app_number] => 547410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3024004 [patent_doc_number] => 05276832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'Computer system having a selectable cache subsystem' [patent_app_type] => 1 [patent_app_number] => 7/541103 [patent_app_country] => US [patent_app_date] => 1990-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 10758 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276832.pdf [firstpage_image] =>[orig_patent_app_number] => 541103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2905116 [patent_doc_number] => 05210850 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-11 [patent_title] => 'Memory address space determination using programmable limit registers with single-ended comparators' [patent_app_type] => 1 [patent_app_number] => 7/538724 [patent_app_country] => US [patent_app_date] => 1990-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9758 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 471 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/210/05210850.pdf [firstpage_image] =>[orig_patent_app_number] => 538724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2930976 [patent_doc_number] => 05206944 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-27 [patent_title] => 'High speed analog to digital converter board for an IBM PC/AT' [patent_app_type] => 1 [patent_app_number] => 7/535002 [patent_app_country] => US [patent_app_date] => 1990-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 8275 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 402 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/206/05206944.pdf [firstpage_image] =>[orig_patent_app_number] => 535002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2948084 [patent_doc_number] => 05247637 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'Method and apparatus for sharing memory in a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 7/531861 [patent_app_country] => US [patent_app_date] => 1990-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4206 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/247/05247637.pdf [firstpage_image] =>[orig_patent_app_number] => 531861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3028300 [patent_doc_number] => 05341483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Dynamic hierarchial associative memory' [patent_app_type] => 1 [patent_app_number] => 7/531506 [patent_app_country] => US [patent_app_date] => 1990-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 33 [patent_no_of_words] => 45681 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341483.pdf [firstpage_image] =>[orig_patent_app_number] => 531506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2718671 [patent_doc_number] => 05062147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-29 [patent_title] => 'User programmable computer monitoring system' [patent_app_type] => 1 [patent_app_number] => 7/529710 [patent_app_country] => US [patent_app_date] => 1990-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 10212 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/062/05062147.pdf [firstpage_image] =>[orig_patent_app_number] => 529710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2864222 [patent_doc_number] => 05134706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-28 [patent_title] => 'Bus interface interrupt apparatus' [patent_app_type] => 1 [patent_app_number] => 7/511873 [patent_app_country] => US [patent_app_date] => 1990-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5038 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 456 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/134/05134706.pdf [firstpage_image] =>[orig_patent_app_number] => 511873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2733798 [patent_doc_number] => 05058007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-15 [patent_title] => 'Next microinstruction generator in a microprogram control unit' [patent_app_type] => 1 [patent_app_number] => 7/515774 [patent_app_country] => US [patent_app_date] => 1990-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3660 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/058/05058007.pdf [firstpage_image] =>[orig_patent_app_number] => 515774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3058657 [patent_doc_number] => 05335325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-02 [patent_title] => 'High-speed packet switching apparatus and method' [patent_app_type] => 1 [patent_app_number] => 7/499182 [patent_app_country] => US [patent_app_date] => 1990-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 79 [patent_figures_cnt] => 79 [patent_no_of_words] => 9900 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/335/05335325.pdf [firstpage_image] =>[orig_patent_app_number] => 499182 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2742651 [patent_doc_number] => 05051889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-24 [patent_title] => 'Page interleaved memory access' [patent_app_type] => 1 [patent_app_number] => 7/490023 [patent_app_country] => US [patent_app_date] => 1990-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3218 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 461 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/051/05051889.pdf [firstpage_image] =>[orig_patent_app_number] => 490023 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2697212 [patent_doc_number] => 05050067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-17 [patent_title] => 'Multiple sliding register stacks in a computer' [patent_app_type] => 1 [patent_app_number] => 7/489722 [patent_app_country] => US [patent_app_date] => 1990-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 8487 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/050/05050067.pdf [firstpage_image] =>[orig_patent_app_number] => 489722 [rel_patent_id] =>[rel_patent_doc_number] =>)