Clifford H. Knoll

Array ( [id] => 9109810 [patent_doc_number] => 20130282942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'Input Output Bridging' [patent_app_type] => utility [patent_app_number] => 13/905750 [patent_app_country] => US [patent_app_date] => 2013-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6451 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13905750 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8769309 [patent_doc_number] => 20130097347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'SYSTEM AND METHOD OF TRANSMITTING DATA BETWEEN DEVICES CONNECTED VIA A BUS DEFINING A TIME SLOT DURING TRANSMISSION FOR RESPONSIVE OUTPUT INFORMATION FROM BUS DEVICES' [patent_app_type] => utility [patent_app_number] => 13/693717 [patent_app_country] => US [patent_app_date] => 2012-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6560 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13693717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8757008 [patent_doc_number] => 20130091313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'METHOD AND APPARATUS FOR DEVICE DYNAMIC ADDITION PROCESSING, AND METHOD AND APPARATUS FOR DEVICE DYNAMIC REMOVAL PROCESSING' [patent_app_type] => utility [patent_app_number] => 13/687811 [patent_app_country] => US [patent_app_date] => 2012-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10294 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13687811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9218370 [patent_doc_number] => 08631180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Requests and data handling in a bus architecture' [patent_app_type] => utility [patent_app_number] => 13/611432 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 12916 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13611432 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8794130 [patent_doc_number] => 20130111099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'PROCESSOR WITH PROGRAMMABLE VIRTUAL PORTS' [patent_app_type] => utility [patent_app_number] => 13/604639 [patent_app_country] => US [patent_app_date] => 2012-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2511 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8511818 [patent_doc_number] => 20120311226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'COMPUTER APPARATUS, COMPUTER SYSTEM AND ADAPTER CARRY-OVER METHOD' [patent_app_type] => utility [patent_app_number] => 13/588554 [patent_app_country] => US [patent_app_date] => 2012-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6882 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13588554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9123637 [patent_doc_number] => 20130290559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'DEADLOCK RESOLUTION IN END-TO-END CREDIT PROTOCOL' [patent_app_type] => utility [patent_app_number] => 13/570377 [patent_app_country] => US [patent_app_date] => 2012-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4012 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13570377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8580778 [patent_doc_number] => 08347008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Method and system for hardware based implementation of USB 1.1 over a high speed link' [patent_app_type] => utility [patent_app_number] => 13/549762 [patent_app_country] => US [patent_app_date] => 2012-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13549762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8574659 [patent_doc_number] => 08341320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'System and method of transmitting data between devices connected via a bus defining a time slot during transmission for responsive output information from bus devices' [patent_app_type] => utility [patent_app_number] => 13/544578 [patent_app_country] => US [patent_app_date] => 2012-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 6507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13544578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9486403 [patent_doc_number] => 08732366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Method to configure serial communications and device thereof' [patent_app_type] => utility [patent_app_number] => 13/459545 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6307 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13459545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9348043 [patent_doc_number] => 08667205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Deadlock resolution in end-to-end credit protocol' [patent_app_type] => utility [patent_app_number] => 13/459548 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4179 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13459548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9006064 [patent_doc_number] => 20130227189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'ELECTRONIC DEVICE WITH BUS SHARING FUNCTION' [patent_app_type] => utility [patent_app_number] => 13/459097 [patent_app_country] => US [patent_app_date] => 2012-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 779 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13459097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9123661 [patent_doc_number] => 20130290583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'System and Method for NUMA-Aware Locking Using Lock Cohorts' [patent_app_type] => utility [patent_app_number] => 13/458871 [patent_app_country] => US [patent_app_date] => 2012-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 36488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13458871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9123660 [patent_doc_number] => 20130290582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'Interconnect Congestion Reduction for Memory-Mapped Peripherals' [patent_app_type] => utility [patent_app_number] => 13/455744 [patent_app_country] => US [patent_app_date] => 2012-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7439 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13455744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8325838 [patent_doc_number] => 20120198249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'Shared Power Domain Dynamic Load Based Power Loss Detection and Notification' [patent_app_type] => utility [patent_app_number] => 13/446717 [patent_app_country] => US [patent_app_date] => 2012-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4530 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13446717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8449081 [patent_doc_number] => 08291148 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-16 [patent_title] => 'Resource virtualization switch' [patent_app_type] => utility [patent_app_number] => 13/445570 [patent_app_country] => US [patent_app_date] => 2012-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 11621 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13445570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8678552 [patent_doc_number] => 08386687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Method and apparatus for data transfer' [patent_app_type] => utility [patent_app_number] => 13/398987 [patent_app_country] => US [patent_app_date] => 2012-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7679 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13398987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8407780 [patent_doc_number] => 20120239848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'MITIGATION OF EMBEDDED CONTROLLER STARVATION IN REAL-TIME SHARED SPI FLASH ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/360746 [patent_app_country] => US [patent_app_date] => 2012-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4572 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13360746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8297221 [patent_doc_number] => 08225020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Method and system for hardware based implementation of USB 1.1 over a high speed link' [patent_app_type] => utility [patent_app_number] => 13/355735 [patent_app_country] => US [patent_app_date] => 2012-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13355735 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8319641 [patent_doc_number] => 08234435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Relay device' [patent_app_type] => utility [patent_app_number] => 13/305832 [patent_app_country] => US [patent_app_date] => 2011-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 41 [patent_no_of_words] => 16378 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13305832 [rel_patent_id] =>[rel_patent_doc_number] =>)