Search

Colleen Erin Snow

Examiner (ID: 16708, Phone: (571)272-8603 , Office: P/2899 )

Most Active Art Unit
2899
Art Unit(s)
2813, 2899
Total Applications
846
Issued Applications
638
Pending Applications
51
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4740012 [patent_doc_number] => 20080233665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/856655 [patent_app_country] => US [patent_app_date] => 2007-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3371 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20080233665.pdf [firstpage_image] =>[orig_patent_app_number] => 11856655 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/856655
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE Sep 16, 2007 Abandoned
Array ( [id] => 4922095 [patent_doc_number] => 20080070410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Method for manufacturing capacitor using system in package' [patent_app_type] => utility [patent_app_number] => 11/898436 [patent_app_country] => US [patent_app_date] => 2007-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1921 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20080070410.pdf [firstpage_image] =>[orig_patent_app_number] => 11898436 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/898436
Method for manufacturing capacitor using system in package Sep 11, 2007 Abandoned
Array ( [id] => 8549130 [patent_doc_number] => 08324011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-04 [patent_title] => 'Implementation of temperature-dependent phase switch layer for improved temperature uniformity during annealing' [patent_app_type] => utility [patent_app_number] => 11/853156 [patent_app_country] => US [patent_app_date] => 2007-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2885 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11853156 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/853156
Implementation of temperature-dependent phase switch layer for improved temperature uniformity during annealing Sep 10, 2007 Issued
Array ( [id] => 5323633 [patent_doc_number] => 20090061623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'METHOD OF FORMING ELECTRICAL CONNECTION STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/850506 [patent_app_country] => US [patent_app_date] => 2007-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2670 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20090061623.pdf [firstpage_image] =>[orig_patent_app_number] => 11850506 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/850506
METHOD OF FORMING ELECTRICAL CONNECTION STRUCTURE Sep 4, 2007 Abandoned
Array ( [id] => 5323646 [patent_doc_number] => 20090061636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'Etching method for nitride semiconductor' [patent_app_type] => utility [patent_app_number] => 11/896515 [patent_app_country] => US [patent_app_date] => 2007-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2486 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20090061636.pdf [firstpage_image] =>[orig_patent_app_number] => 11896515 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/896515
Etching method for nitride semiconductor Sep 3, 2007 Issued
Array ( [id] => 4624223 [patent_doc_number] => 08003519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Systems and methods for back end of line processing of semiconductor circuits' [patent_app_type] => utility [patent_app_number] => 11/847135 [patent_app_country] => US [patent_app_date] => 2007-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2376 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/003/08003519.pdf [firstpage_image] =>[orig_patent_app_number] => 11847135 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/847135
Systems and methods for back end of line processing of semiconductor circuits Aug 28, 2007 Issued
Array ( [id] => 4944118 [patent_doc_number] => 20080081443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Method for fabricating semiconductor' [patent_app_type] => utility [patent_app_number] => 11/892855 [patent_app_country] => US [patent_app_date] => 2007-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3872 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20080081443.pdf [firstpage_image] =>[orig_patent_app_number] => 11892855 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/892855
Method for fabricating semiconductor Aug 27, 2007 Abandoned
Array ( [id] => 4451604 [patent_doc_number] => 07964929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Method and apparatus providing imager pixels with shared pixel components' [patent_app_type] => utility [patent_app_number] => 11/892516 [patent_app_country] => US [patent_app_date] => 2007-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6383 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/964/07964929.pdf [firstpage_image] =>[orig_patent_app_number] => 11892516 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/892516
Method and apparatus providing imager pixels with shared pixel components Aug 22, 2007 Issued
Array ( [id] => 5337434 [patent_doc_number] => 20090053898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'Formation of a slot in a silicon substrate' [patent_app_type] => utility [patent_app_number] => 11/894316 [patent_app_country] => US [patent_app_date] => 2007-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1226 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20090053898.pdf [firstpage_image] =>[orig_patent_app_number] => 11894316 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/894316
Formation of a slot in a silicon substrate Aug 20, 2007 Issued
Array ( [id] => 4733916 [patent_doc_number] => 20080050895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Method for Manufacturing Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 11/840435 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 50021 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20080050895.pdf [firstpage_image] =>[orig_patent_app_number] => 11840435 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/840435
Method for manufacturing semiconductor device Aug 16, 2007 Issued
Array ( [id] => 4733916 [patent_doc_number] => 20080050895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Method for Manufacturing Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 11/840435 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 50021 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20080050895.pdf [firstpage_image] =>[orig_patent_app_number] => 11840435 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/840435
Method for manufacturing semiconductor device Aug 16, 2007 Issued
Array ( [id] => 4822038 [patent_doc_number] => 20080227233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR OPTICAL DEVICE' [patent_app_type] => utility [patent_app_number] => 11/837676 [patent_app_country] => US [patent_app_date] => 2007-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2669 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20080227233.pdf [firstpage_image] =>[orig_patent_app_number] => 11837676 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/837676
Method for manufacturing semiconductor optical device Aug 12, 2007 Issued
Array ( [id] => 6590062 [patent_doc_number] => 20100001264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'INSULATING LAYER, ELECTRONIC DEVICE, FIELD EFFECT TRANSISTOR, AND POLYVINYLTHIOPHENOL' [patent_app_type] => utility [patent_app_number] => 12/376123 [patent_app_country] => US [patent_app_date] => 2007-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 13585 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20100001264.pdf [firstpage_image] =>[orig_patent_app_number] => 12376123 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/376123
Insulating layer, electronic device, field effect transistor, and polyvinylthiophenol Aug 1, 2007 Issued
Array ( [id] => 4688317 [patent_doc_number] => 20080032498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'METHOD FOR FABRICATING METAL LINE OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/831726 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2423 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20080032498.pdf [firstpage_image] =>[orig_patent_app_number] => 11831726 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/831726
METHOD FOR FABRICATING METAL LINE OF SEMICONDUCTOR DEVICE Jul 30, 2007 Abandoned
Array ( [id] => 43680 [patent_doc_number] => 07776704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Method to build self-aligned NPN in advanced BiCMOS technology' [patent_app_type] => utility [patent_app_number] => 11/830376 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4537 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/776/07776704.pdf [firstpage_image] =>[orig_patent_app_number] => 11830376 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830376
Method to build self-aligned NPN in advanced BiCMOS technology Jul 29, 2007 Issued
Array ( [id] => 5162992 [patent_doc_number] => 20070284572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'POLYTHIOPHENES AND DEVICES THEREOF' [patent_app_type] => utility [patent_app_number] => 11/782812 [patent_app_country] => US [patent_app_date] => 2007-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6541 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20070284572.pdf [firstpage_image] =>[orig_patent_app_number] => 11782812 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/782812
Polythiophenes and devices thereof Jul 24, 2007 Issued
Array ( [id] => 5455990 [patent_doc_number] => 20090256142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-15 [patent_title] => 'ORGANIC THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 12/375283 [patent_app_country] => US [patent_app_date] => 2007-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10567 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20090256142.pdf [firstpage_image] =>[orig_patent_app_number] => 12375283 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/375283
ORGANIC THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING SAME Jul 16, 2007 Abandoned
Array ( [id] => 5225173 [patent_doc_number] => 20070254439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'METHOD FOR MAKING SEMICONDUCTOR TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 11/772823 [patent_app_country] => US [patent_app_date] => 2007-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1852 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20070254439.pdf [firstpage_image] =>[orig_patent_app_number] => 11772823 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/772823
METHOD FOR MAKING SEMICONDUCTOR TRANSISTOR Jul 2, 2007 Abandoned
Array ( [id] => 4538888 [patent_doc_number] => 07875478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Method for controlling color contrast of a multi-wavelength light-emitting diode' [patent_app_type] => utility [patent_app_number] => 11/819175 [patent_app_country] => US [patent_app_date] => 2007-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1726 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/875/07875478.pdf [firstpage_image] =>[orig_patent_app_number] => 11819175 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/819175
Method for controlling color contrast of a multi-wavelength light-emitting diode Jun 25, 2007 Issued
Array ( [id] => 4803141 [patent_doc_number] => 20080014729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Method of manufacturing a memory device' [patent_app_type] => utility [patent_app_number] => 11/820516 [patent_app_country] => US [patent_app_date] => 2007-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5810 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20080014729.pdf [firstpage_image] =>[orig_patent_app_number] => 11820516 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/820516
Method of manufacturing a memory device Jun 19, 2007 Abandoned
Menu