Search

Colleen Erin Snow

Examiner (ID: 16708, Phone: (571)272-8603 , Office: P/2899 )

Most Active Art Unit
2899
Art Unit(s)
2813, 2899
Total Applications
846
Issued Applications
638
Pending Applications
51
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7005340 [patent_doc_number] => 20050170653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Semiconductor manufacturing method and apparatus' [patent_app_type] => utility [patent_app_number] => 11/088976 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2677 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20050170653.pdf [firstpage_image] =>[orig_patent_app_number] => 11088976 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/088976
Semiconductor manufacturing method and apparatus Mar 23, 2005 Abandoned
Array ( [id] => 6966684 [patent_doc_number] => 20050233581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/085135 [patent_app_country] => US [patent_app_date] => 2005-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8819 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20050233581.pdf [firstpage_image] =>[orig_patent_app_number] => 11085135 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/085135
Method for manufacturing semiconductor device Mar 21, 2005 Issued
Array ( [id] => 5697552 [patent_doc_number] => 20060214236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'SEMICONDUCTOR TRANSISTOR AND METHOD FOR MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 10/907125 [patent_app_country] => US [patent_app_date] => 2005-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1828 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20060214236.pdf [firstpage_image] =>[orig_patent_app_number] => 10907125 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/907125
Semiconductor transistor Mar 21, 2005 Issued
Array ( [id] => 5760292 [patent_doc_number] => 20060211237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Method and apparatus for planarizing gap-filling material' [patent_app_type] => utility [patent_app_number] => 11/085295 [patent_app_country] => US [patent_app_date] => 2005-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2255 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20060211237.pdf [firstpage_image] =>[orig_patent_app_number] => 11085295 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/085295
Method and apparatus for planarizing gap-filling material Mar 20, 2005 Abandoned
Array ( [id] => 5760309 [patent_doc_number] => 20060211254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Top patterned hardmask and method for patterning' [patent_app_type] => utility [patent_app_number] => 11/084495 [patent_app_country] => US [patent_app_date] => 2005-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2493 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20060211254.pdf [firstpage_image] =>[orig_patent_app_number] => 11084495 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/084495
Top patterned hardmask and method for patterning Mar 17, 2005 Issued
Array ( [id] => 5760212 [patent_doc_number] => 20060211157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Novel CMP endpoint detection process' [patent_app_type] => utility [patent_app_number] => 11/082406 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4575 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20060211157.pdf [firstpage_image] =>[orig_patent_app_number] => 11082406 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/082406
Novel CMP endpoint detection process Mar 16, 2005 Abandoned
Array ( [id] => 9582175 [patent_doc_number] => 08772178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-08 [patent_title] => 'Technique for forming a dielectric interlayer above a structure including closely spaced lines' [patent_app_type] => utility [patent_app_number] => 11/082156 [patent_app_country] => US [patent_app_date] => 2005-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 6356 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11082156 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/082156
Technique for forming a dielectric interlayer above a structure including closely spaced lines Mar 15, 2005 Issued
Array ( [id] => 322492 [patent_doc_number] => 07517724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Dicing/die bonding sheet' [patent_app_type] => utility [patent_app_number] => 10/556535 [patent_app_country] => US [patent_app_date] => 2005-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 10653 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/517/07517724.pdf [firstpage_image] =>[orig_patent_app_number] => 10556535 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/556535
Dicing/die bonding sheet Mar 14, 2005 Issued
Array ( [id] => 5596449 [patent_doc_number] => 20060160366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'Method for preparing a structure with high aspect ratio' [patent_app_type] => utility [patent_app_number] => 11/078435 [patent_app_country] => US [patent_app_date] => 2005-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2229 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20060160366.pdf [firstpage_image] =>[orig_patent_app_number] => 11078435 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/078435
Method for preparing a structure with high aspect ratio Mar 13, 2005 Issued
Array ( [id] => 5780144 [patent_doc_number] => 20060202239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'METHODS FOR PROVIDING GATE CONDUCTORS ON SEMICONDUCTORS AND SEMICONDUCTORS FORMED THEREBY' [patent_app_type] => utility [patent_app_number] => 10/906876 [patent_app_country] => US [patent_app_date] => 2005-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3231 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20060202239.pdf [firstpage_image] =>[orig_patent_app_number] => 10906876 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/906876
Methods for providing gate conductors on semiconductors and semiconductors formed thereby Mar 9, 2005 Issued
Array ( [id] => 7590961 [patent_doc_number] => 07663200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Integrated circuit device packaging structure and packaging method' [patent_app_type] => utility [patent_app_number] => 11/073726 [patent_app_country] => US [patent_app_date] => 2005-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3148 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/663/07663200.pdf [firstpage_image] =>[orig_patent_app_number] => 11073726 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/073726
Integrated circuit device packaging structure and packaging method Mar 7, 2005 Issued
Array ( [id] => 852964 [patent_doc_number] => 07378348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-27 [patent_title] => 'Polishing compound for insulating film for semiconductor integrated circuit and method for producing semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/071182 [patent_app_country] => US [patent_app_date] => 2005-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8320 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/378/07378348.pdf [firstpage_image] =>[orig_patent_app_number] => 11071182 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/071182
Polishing compound for insulating film for semiconductor integrated circuit and method for producing semiconductor integrated circuit Mar 3, 2005 Issued
Array ( [id] => 823613 [patent_doc_number] => 07405157 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-29 [patent_title] => 'Methods for the electrochemical deposition of copper onto a barrier layer of a work piece' [patent_app_type] => utility [patent_app_number] => 11/071135 [patent_app_country] => US [patent_app_date] => 2005-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 5714 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/405/07405157.pdf [firstpage_image] =>[orig_patent_app_number] => 11071135 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/071135
Methods for the electrochemical deposition of copper onto a barrier layer of a work piece Mar 1, 2005 Issued
Array ( [id] => 292693 [patent_doc_number] => 07544987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-09 [patent_title] => 'High-k dielectric materials and processes for manufacturing them' [patent_app_type] => utility [patent_app_number] => 11/070415 [patent_app_country] => US [patent_app_date] => 2005-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2857 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/544/07544987.pdf [firstpage_image] =>[orig_patent_app_number] => 11070415 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/070415
High-k dielectric materials and processes for manufacturing them Mar 1, 2005 Issued
Array ( [id] => 5680916 [patent_doc_number] => 20060197183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'IMPROVED MIM CAPACITOR STRUCTURE AND PROCESS' [patent_app_type] => utility [patent_app_number] => 10/906666 [patent_app_country] => US [patent_app_date] => 2005-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2868 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20060197183.pdf [firstpage_image] =>[orig_patent_app_number] => 10906666 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/906666
IMPROVED MIM CAPACITOR STRUCTURE AND PROCESS Feb 28, 2005 Abandoned
Array ( [id] => 5664726 [patent_doc_number] => 20060170076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Apparatus, system, and method for reducing integrated circuit peeling' [patent_app_type] => utility [patent_app_number] => 11/049065 [patent_app_country] => US [patent_app_date] => 2005-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3625 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20060170076.pdf [firstpage_image] =>[orig_patent_app_number] => 11049065 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/049065
Apparatus, system, and method for reducing integrated circuit peeling Feb 1, 2005 Abandoned
Array ( [id] => 813704 [patent_doc_number] => 07413976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Uniform passivation method for conductive features' [patent_app_type] => utility [patent_app_number] => 11/047836 [patent_app_country] => US [patent_app_date] => 2005-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 5356 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/413/07413976.pdf [firstpage_image] =>[orig_patent_app_number] => 11047836 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/047836
Uniform passivation method for conductive features Jan 31, 2005 Issued
Array ( [id] => 606422 [patent_doc_number] => 07153787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-26 [patent_title] => 'CVD plasma assisted lower dielectric constant SICOH film' [patent_app_type] => utility [patent_app_number] => 11/044246 [patent_app_country] => US [patent_app_date] => 2005-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 7353 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/153/07153787.pdf [firstpage_image] =>[orig_patent_app_number] => 11044246 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/044246
CVD plasma assisted lower dielectric constant SICOH film Jan 26, 2005 Issued
Array ( [id] => 891948 [patent_doc_number] => 07344953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Process for vertically patterning substrates in semiconductor process technology by means of inconformal deposition' [patent_app_type] => utility [patent_app_number] => 11/042326 [patent_app_country] => US [patent_app_date] => 2005-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6859 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/344/07344953.pdf [firstpage_image] =>[orig_patent_app_number] => 11042326 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/042326
Process for vertically patterning substrates in semiconductor process technology by means of inconformal deposition Jan 25, 2005 Issued
Array ( [id] => 4639990 [patent_doc_number] => 08018017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Thermo-mechanical cleavable structure' [patent_app_type] => utility [patent_app_number] => 10/905905 [patent_app_country] => US [patent_app_date] => 2005-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6013 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/018/08018017.pdf [firstpage_image] =>[orig_patent_app_number] => 10905905 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/905905
Thermo-mechanical cleavable structure Jan 25, 2005 Issued
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