
Colleen Erin Snow
Examiner (ID: 16708, Phone: (571)272-8603 , Office: P/2899 )
| Most Active Art Unit | 2899 |
| Art Unit(s) | 2813, 2899 |
| Total Applications | 846 |
| Issued Applications | 638 |
| Pending Applications | 51 |
| Abandoned Applications | 177 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6988619
[patent_doc_number] => 20050087751
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'Insulating nitride layer and process for its forming, and semiconductor device and process for its production'
[patent_app_type] => utility
[patent_app_number] => 10/990116
[patent_app_country] => US
[patent_app_date] => 2004-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 4423
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0087/20050087751.pdf
[firstpage_image] =>[orig_patent_app_number] => 10990116
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/990116 | Insulating nitride layer and process for its forming, and semiconductor device and process for its production | Nov 15, 2004 | Abandoned |
Array
(
[id] => 7178915
[patent_doc_number] => 20050124162
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Fabrication method for a hard mask on a semiconductor structure'
[patent_app_type] => utility
[patent_app_number] => 10/988346
[patent_app_country] => US
[patent_app_date] => 2004-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1363
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20050124162.pdf
[firstpage_image] =>[orig_patent_app_number] => 10988346
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/988346 | Fabrication method for a hard mask on a semiconductor structure | Nov 11, 2004 | Abandoned |
Array
(
[id] => 5807891
[patent_doc_number] => 20060094246
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'METHOD OF WAFER PATTERNING FOR REDUCING EDGE EXCLUSION ZONE'
[patent_app_type] => utility
[patent_app_number] => 10/980945
[patent_app_country] => US
[patent_app_date] => 2004-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3959
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0094/20060094246.pdf
[firstpage_image] =>[orig_patent_app_number] => 10980945
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/980945 | Method of wafer patterning for reducing edge exclusion zone | Nov 2, 2004 | Issued |
Array
(
[id] => 6991047
[patent_doc_number] => 20050090084
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'Method of forming a gate structure'
[patent_app_type] => utility
[patent_app_number] => 10/968105
[patent_app_country] => US
[patent_app_date] => 2004-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1511
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0090/20050090084.pdf
[firstpage_image] =>[orig_patent_app_number] => 10968105
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/968105 | Method of forming a gate structure | Oct 19, 2004 | Abandoned |
Array
(
[id] => 5814178
[patent_doc_number] => 20060084217
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-20
[patent_title] => 'Plasma impurification of a metal gate in a semiconductor fabrication process'
[patent_app_type] => utility
[patent_app_number] => 10/969486
[patent_app_country] => US
[patent_app_date] => 2004-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3202
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0084/20060084217.pdf
[firstpage_image] =>[orig_patent_app_number] => 10969486
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/969486 | Plasma impurification of a metal gate in a semiconductor fabrication process | Oct 19, 2004 | Abandoned |
Array
(
[id] => 467423
[patent_doc_number] => 07235493
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-26
[patent_title] => 'Low-k dielectric process for multilevel interconnection using mircocavity engineering during electric circuit manufacture'
[patent_app_type] => utility
[patent_app_number] => 10/968786
[patent_app_country] => US
[patent_app_date] => 2004-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 4041
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/235/07235493.pdf
[firstpage_image] =>[orig_patent_app_number] => 10968786
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/968786 | Low-k dielectric process for multilevel interconnection using mircocavity engineering during electric circuit manufacture | Oct 17, 2004 | Issued |
Array
(
[id] => 5814288
[patent_doc_number] => 20060084276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-20
[patent_title] => 'Methods for surface treatment and structure formed therefrom'
[patent_app_type] => utility
[patent_app_number] => 10/965575
[patent_app_country] => US
[patent_app_date] => 2004-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1651
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0084/20060084276.pdf
[firstpage_image] =>[orig_patent_app_number] => 10965575
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/965575 | Methods for surface treatment and structure formed therefrom | Oct 13, 2004 | Abandoned |
Array
(
[id] => 5718440
[patent_doc_number] => 20060071213
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-06
[patent_title] => 'Low temperature selective epitaxial growth of silicon germanium layers'
[patent_app_type] => utility
[patent_app_number] => 10/957791
[patent_app_country] => US
[patent_app_date] => 2004-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1346
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0071/20060071213.pdf
[firstpage_image] =>[orig_patent_app_number] => 10957791
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/957791 | Low temperature selective epitaxial growth of silicon germanium layers | Oct 3, 2004 | Abandoned |
Array
(
[id] => 5720898
[patent_doc_number] => 20060073673
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-06
[patent_title] => 'Ammonium hydroxide treatments for semiconductor substrates'
[patent_app_type] => utility
[patent_app_number] => 10/958126
[patent_app_country] => US
[patent_app_date] => 2004-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5305
[patent_no_of_claims] => 50
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0073/20060073673.pdf
[firstpage_image] =>[orig_patent_app_number] => 10958126
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/958126 | Ammonium hydroxide treatments for semiconductor substrates | Oct 3, 2004 | Issued |
Array
(
[id] => 508954
[patent_doc_number] => 07199029
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-03
[patent_title] => 'Selective deposition of ZnO nanostructures on a silicon substrate using a nickel catalyst and either patterned polysilicon or silicon surface modification'
[patent_app_type] => utility
[patent_app_number] => 10/956786
[patent_app_country] => US
[patent_app_date] => 2004-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 2086
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/199/07199029.pdf
[firstpage_image] =>[orig_patent_app_number] => 10956786
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/956786 | Selective deposition of ZnO nanostructures on a silicon substrate using a nickel catalyst and either patterned polysilicon or silicon surface modification | Sep 30, 2004 | Issued |
Array
(
[id] => 7252877
[patent_doc_number] => 20050074948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-07
[patent_title] => 'Method of manufacturing shallow trench isolation structure using HF vapor etching process'
[patent_app_type] => utility
[patent_app_number] => 10/949426
[patent_app_country] => US
[patent_app_date] => 2004-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4107
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0074/20050074948.pdf
[firstpage_image] =>[orig_patent_app_number] => 10949426
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/949426 | Method of manufacturing shallow trench isolation structure using HF vapor etching process | Sep 23, 2004 | Abandoned |
Array
(
[id] => 5724131
[patent_doc_number] => 20060054891
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-16
[patent_title] => 'Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques'
[patent_app_type] => utility
[patent_app_number] => 10/939736
[patent_app_country] => US
[patent_app_date] => 2004-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6073
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0054/20060054891.pdf
[firstpage_image] =>[orig_patent_app_number] => 10939736
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/939736 | Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques | Sep 12, 2004 | Issued |
Array
(
[id] => 7212599
[patent_doc_number] => 20050054143
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-10
[patent_title] => 'Using benzocyclobutene based polymers as underfill materials'
[patent_app_type] => utility
[patent_app_number] => 10/939226
[patent_app_country] => US
[patent_app_date] => 2004-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1223
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0054/20050054143.pdf
[firstpage_image] =>[orig_patent_app_number] => 10939226
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/939226 | Using benzocyclobutene based polymers as underfill materials | Sep 9, 2004 | Abandoned |
Array
(
[id] => 5898223
[patent_doc_number] => 20060043456
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-02
[patent_title] => 'Protection of tunnel dielectric using epitaxial silicon'
[patent_app_type] => utility
[patent_app_number] => 10/932795
[patent_app_country] => US
[patent_app_date] => 2004-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5181
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0043/20060043456.pdf
[firstpage_image] =>[orig_patent_app_number] => 10932795
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/932795 | Protection of tunnel dielectric using epitaxial silicon | Sep 1, 2004 | Issued |
Array
(
[id] => 541821
[patent_doc_number] => 07169659
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-30
[patent_title] => 'Method to selectively recess ETCH regions on a wafer surface using capoly as a mask'
[patent_app_type] => utility
[patent_app_number] => 10/931195
[patent_app_country] => US
[patent_app_date] => 2004-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 20
[patent_no_of_words] => 5458
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/169/07169659.pdf
[firstpage_image] =>[orig_patent_app_number] => 10931195
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/931195 | Method to selectively recess ETCH regions on a wafer surface using capoly as a mask | Aug 30, 2004 | Issued |
Array
(
[id] => 7147707
[patent_doc_number] => 20050023579
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-03
[patent_title] => 'Semiconductor Device and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/930475
[patent_app_country] => US
[patent_app_date] => 2004-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 18582
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0023/20050023579.pdf
[firstpage_image] =>[orig_patent_app_number] => 10930475
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/930475 | Semiconductor device and method of fabricating the same | Aug 30, 2004 | Issued |
Array
(
[id] => 7162167
[patent_doc_number] => 20050199980
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-15
[patent_title] => 'Semiconductor device and method of manufacturing same'
[patent_app_type] => utility
[patent_app_number] => 10/929475
[patent_app_country] => US
[patent_app_date] => 2004-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4726
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0199/20050199980.pdf
[firstpage_image] =>[orig_patent_app_number] => 10929475
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/929475 | Semiconductor device and method of manufacturing same | Aug 30, 2004 | Issued |
Array
(
[id] => 538630
[patent_doc_number] => 07173285
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-06
[patent_title] => 'Lithographic methods to reduce stacking fault nucleation sites'
[patent_app_type] => utility
[patent_app_number] => 10/929226
[patent_app_country] => US
[patent_app_date] => 2004-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 20
[patent_no_of_words] => 8588
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/173/07173285.pdf
[firstpage_image] =>[orig_patent_app_number] => 10929226
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/929226 | Lithographic methods to reduce stacking fault nucleation sites | Aug 29, 2004 | Issued |
Array
(
[id] => 7147835
[patent_doc_number] => 20050023623
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-03
[patent_title] => 'Gate structure and method'
[patent_app_type] => utility
[patent_app_number] => 10/928036
[patent_app_country] => US
[patent_app_date] => 2004-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2640
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0023/20050023623.pdf
[firstpage_image] =>[orig_patent_app_number] => 10928036
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/928036 | Gate structure and method | Aug 26, 2004 | Abandoned |
Array
(
[id] => 7083394
[patent_doc_number] => 20050048774
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-03
[patent_title] => 'Method for manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/925988
[patent_app_country] => US
[patent_app_date] => 2004-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4762
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0048/20050048774.pdf
[firstpage_image] =>[orig_patent_app_number] => 10925988
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/925988 | Method for manufacturing semiconductor device | Aug 25, 2004 | Abandoned |