Colleen J. O. Toole

Array ( [id] => 16448978 [patent_doc_number] => 10840913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Circuits, apparatuses, and methods for frequency division [patent_app_type] => utility [patent_app_number] => 16/220489 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6461 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220489 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15371067 [patent_doc_number] => 20200021298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => INTEGRATED CIRCUIT INCLUDING PHASE LOCKED LOOP CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/216226 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16216226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14477731 [patent_doc_number] => 20190190518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => SYSTEMS FOR CONTROLLING A SLEW RATE OF A SWITCH [patent_app_type] => utility [patent_app_number] => 16/216805 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16216805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18175647 [patent_doc_number] => 11575373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Switch circuitry [patent_app_type] => utility [patent_app_number] => 16/213185 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4019 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16213185 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17773064 [patent_doc_number] => 11405022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Filter networks for driving capacitive loads [patent_app_type] => utility [patent_app_number] => 16/209832 [patent_app_country] => US [patent_app_date] => 2018-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16209832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15599755 [patent_doc_number] => 20200076412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => DUTY CYCLE CORRECTION FOR COMPLEMENTARY CLOCK SIGNALS [patent_app_type] => utility [patent_app_number] => 16/206321 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16206321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16002647 [patent_doc_number] => 20200177194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => Fractional frequency synthesis by sigma-delta modulating frequency of a reference clock [patent_app_type] => utility [patent_app_number] => 16/205308 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16205308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14383769 [patent_doc_number] => 20190165797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => FREQUENCY LOCKED LOOP WITH FAST REACTION TIME [patent_app_type] => utility [patent_app_number] => 16/201244 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16201244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15907813 [patent_doc_number] => 20200153427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => Driving D-Mode FETS in Half-Bridge Driver Configuration [patent_app_type] => utility [patent_app_number] => 16/186323 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16186323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15772427 [patent_doc_number] => 20200117231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => METHOD AND APPARATUS FOR TRANSACTION BASED PROPAGATED CLOCK-GATING FOR LOW POWER DESIGN [patent_app_type] => utility [patent_app_number] => 16/160075 [patent_app_country] => US [patent_app_date] => 2018-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16160075 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15457063 [patent_doc_number] => 20200041356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => METHODS AND APPARATUS TO PROVIDE AN ADAPTIVE GATE DRIVER FOR SWITCHING DEVICES [patent_app_type] => utility [patent_app_number] => 16/050949 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15462307 [patent_doc_number] => 20200043978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => MAGNETIC FIELD CONTROLLED TRANSISTOR [patent_app_type] => utility [patent_app_number] => 16/051457 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4119 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16051457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13572241 [patent_doc_number] => 20180337668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => SEMICONDUCTOR MODULE, SWITCHING ELEMENT SELECTING METHOD USED FOR SEMICONDUCTOR MODULE, AND CHIP DESIGNING METHOD FOR SWITCHING ELEMENT [patent_app_type] => utility [patent_app_number] => 16/049049 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5011 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16049049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16684867 [patent_doc_number] => 10944362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Coupling surface acoustic wave resonators to a Josephson ring modulator [patent_app_type] => utility [patent_app_number] => 16/048935 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14146 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16048935 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14632673 [patent_doc_number] => 20190229709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => SWITCHED-CAPACITOR FILTER WITH GLITCH REDUCTION [patent_app_type] => utility [patent_app_number] => 16/046581 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13880355 [patent_doc_number] => 20190036518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => COMPARATOR CIRCUIT, CORRESPONDING DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 16/043346 [patent_app_country] => US [patent_app_date] => 2018-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16043346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14632709 [patent_doc_number] => 20190229727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => CONTROL CIRCUIT FOR AN H-BRIDGE CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/029277 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16029277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16610028 [patent_doc_number] => 10911053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Phase locked loop design with reduced VCO gain [patent_app_type] => utility [patent_app_number] => 15/966134 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2900 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15966134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14838981 [patent_doc_number] => 20190277891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => LOW POWER COMPARATOR AND SELF-REGULATED DEVICE [patent_app_type] => utility [patent_app_number] => 15/965994 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3349 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15965994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15047015 [patent_doc_number] => 20190334512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => Voltage-Controlled Delay Generator [patent_app_type] => utility [patent_app_number] => 15/966939 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15966939 [rel_patent_id] =>[rel_patent_doc_number] =>)