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Congvan Tran

Examiner (ID: 16042, Phone: (571)272-7871 , Office: P/2645 )

Most Active Art Unit
2647
Art Unit(s)
2683, 2746, 2733, 2607, 2641, 2617, 2645, 2647, 2688
Total Applications
2244
Issued Applications
1894
Pending Applications
162
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19686100 [patent_doc_number] => 20250004645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/886901 [patent_app_country] => US [patent_app_date] => 2024-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18886901 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/886901
COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY DEVICE Sep 15, 2024 Pending
Array ( [id] => 19618911 [patent_doc_number] => 20240404591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => RADIATION HARDENED E-FUSE MACRO [patent_app_type] => utility [patent_app_number] => 18/800530 [patent_app_country] => US [patent_app_date] => 2024-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18800530 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/800530
RADIATION HARDENED E-FUSE MACRO Aug 11, 2024 Pending
Array ( [id] => 19546650 [patent_doc_number] => 20240363686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/767734 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767734 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767734
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Jul 8, 2024 Pending
Array ( [id] => 19531465 [patent_doc_number] => 20240355367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => TEMPERATURE DIFFERENTIAL-BASED VOLTAGE OFFSET CONTROL [patent_app_type] => utility [patent_app_number] => 18/760918 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760918 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760918
TEMPERATURE DIFFERENTIAL-BASED VOLTAGE OFFSET CONTROL Jun 30, 2024 Pending
Array ( [id] => 20422843 [patent_doc_number] => 20250384928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => MEMORY DEVICE, METHOD OF MANUFACTURING, AND METHOD OF OPERATING [patent_app_type] => utility [patent_app_number] => 18/745121 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745121 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/745121
MEMORY DEVICE, METHOD OF MANUFACTURING, AND METHOD OF OPERATING Jun 16, 2024 Pending
Array ( [id] => 19483713 [patent_doc_number] => 20240331755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => HIGH-DENSITY MEMORY CELLS AND LAYOUTS THEREOF [patent_app_type] => utility [patent_app_number] => 18/743529 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743529 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743529
HIGH-DENSITY MEMORY CELLS AND LAYOUTS THEREOF Jun 13, 2024 Pending
Array ( [id] => 19574865 [patent_doc_number] => 20240379157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => CONFIGURABLE RESISTIVITY FOR LINES IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/741193 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741193 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741193
CONFIGURABLE RESISTIVITY FOR LINES IN A MEMORY DEVICE Jun 11, 2024 Pending
Array ( [id] => 19483743 [patent_doc_number] => 20240331785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/739530 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739530 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739530
NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF Jun 10, 2024 Pending
Array ( [id] => 19646244 [patent_doc_number] => 20240420764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/732967 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23485 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18732967 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/732967
MEMORY DEVICE Jun 3, 2024 Pending
Array ( [id] => 20399362 [patent_doc_number] => 20250374837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/675159 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675159 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675159
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF May 27, 2024 Pending
Array ( [id] => 19420771 [patent_doc_number] => 20240296895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 18/662238 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 119743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 579 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662238
SEMICONDUCTOR MEMORY May 12, 2024 Pending
Array ( [id] => 20088574 [patent_doc_number] => 20250218510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/651539 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18651539 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/651539
SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE Apr 29, 2024 Pending
Array ( [id] => 19348885 [patent_doc_number] => 20240257849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/630352 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630352 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/630352
STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE Apr 8, 2024 Pending
Array ( [id] => 19348923 [patent_doc_number] => 20240257887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => ACCELERATING CONFIGURATION UPDATES FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/630983 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8504 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630983 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/630983
ACCELERATING CONFIGURATION UPDATES FOR MEMORY DEVICES Apr 8, 2024 Pending
Array ( [id] => 20028479 [patent_doc_number] => 20250166701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => SEMICONDUCTOR DEVICE AND OPERATING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/623336 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623336 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623336
SEMICONDUCTOR DEVICE AND OPERATING METHOD OF THE SAME Mar 31, 2024 Pending
Array ( [id] => 20283368 [patent_doc_number] => 20250308610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => BUILT-IN SELF-TEST CIRCUITRY FOR DATA IN PATH FOR NON-VOLATILE MEMORY WITH MULTIPLE TEST CLOCK SPEEDS FOR MULTIPLE TEST MODES [patent_app_type] => utility [patent_app_number] => 18/619466 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18619466 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/619466
Built-in self-test circuitry for data in path for non-volatile memory with multiple test clock speeds for multiple test modes Mar 27, 2024 Issued
Array ( [id] => 19452410 [patent_doc_number] => 20240312540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING WORDLINES [patent_app_type] => utility [patent_app_number] => 18/599471 [patent_app_country] => US [patent_app_date] => 2024-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18599471 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/599471
MEMORY DEVICE AND METHOD OF OPERATING WORDLINES Mar 7, 2024 Pending
Array ( [id] => 19335345 [patent_doc_number] => 20240249775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/591728 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591728 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591728
Semiconductor device and data storage system including the same Feb 28, 2024 Issued
Array ( [id] => 19252511 [patent_doc_number] => 20240203508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => SELECTIVE MANAGEMENT OF ERASE OPERATIONS IN MEMORY DEVICES THAT ENABLE SUSPEND COMMANDS [patent_app_type] => utility [patent_app_number] => 18/589730 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18589730 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/589730
SELECTIVE MANAGEMENT OF ERASE OPERATIONS IN MEMORY DEVICES THAT ENABLE SUSPEND COMMANDS Feb 27, 2024 Pending
Array ( [id] => 19237077 [patent_doc_number] => 20240194272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => METHOD AND SYSTEM FOR ACCESSING MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/586134 [patent_app_country] => US [patent_app_date] => 2024-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18586134 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/586134
METHOD AND SYSTEM FOR ACCESSING MEMORY CELLS Feb 22, 2024 Pending
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